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<DU-CELL xmlns="http://www.yunzhiruantong.com/yzrt/yzmm/du-cell">

  <BASE>

    <NR_PCI>248</NR_PCI>

    <NR_CELL_NUM>1</NR_CELL_NUM>

    <NR_CELL_ID>1</NR_CELL_ID>

    <TAG_MCC_0>0</TAG_MCC_0>

    <TAG_MCC_1>0</TAG_MCC_1>

    <TAG_MCC_2>1</TAG_MCC_2>

    <TAG_MNC_0>0</TAG_MNC_0>

    <TAG_MNC_1>1</TAG_MNC_1>

    <TAG_MNC_2>255</TAG_MNC_2>

    <NR_UE_MAX_DL_RANK>2</NR_UE_MAX_DL_RANK>

    <NR_UE_MAX_UL_RANK>2</NR_UE_MAX_UL_RANK>

    <NR_UE_PTRS_ENABLE>false</NR_UE_PTRS_ENABLE>

    <NR_DL_NUM_OF_ANT_PORTS>4</NR_DL_NUM_OF_ANT_PORTS>

    <NR_UL_NUM_OF_ANT_PORTS>2</NR_UL_NUM_OF_ANT_PORTS>

    <NR_DL_MODULATION>1</NR_DL_MODULATION>

    <NR_UL_MODULATION>1</NR_UL_MODULATION>

    <NR_UL_CHN_BW>10</NR_UL_CHN_BW>

    <NR_DL_CHN_BW>10</NR_DL_CHN_BW>

    <NR_MODE_TYPE>TDD</NR_MODE_TYPE>

    <NR_CELL_FAPI_UDP_MESSAGE>0</NR_CELL_FAPI_UDP_MESSAGE>

	<NR_CELL_STATUS>0</NR_CELL_STATUS>

  </BASE>

  <PRU_CONFIG>

    <NR_CELL_PRU_TX_FREQ>2566170</NR_CELL_PRU_TX_FREQ>

    <NR_CELL_PRU_RX_FREQ>2566170</NR_CELL_PRU_RX_FREQ>

    <NR_CELL_PRU_AUX_FREQ>0</NR_CELL_PRU_AUX_FREQ>

    <NR_CELL_PRU_TX_MAX_POWER>43</NR_CELL_PRU_TX_MAX_POWER>

    <NR_CELL_PRU_RX_GAIN>255</NR_CELL_PRU_RX_GAIN>

    <NR_CELL_PRU_SAMPLE_RATE>122880</NR_CELL_PRU_SAMPLE_RATE>

    <NR_CELL_PRU_WIDEBAND>100</NR_CELL_PRU_WIDEBAND>

    <NR_CELL_PRU_TX_ANTNUMBER>4</NR_CELL_PRU_TX_ANTNUMBER>

    <NR_CELL_PRU_RX_ANTNUMBER>4</NR_CELL_PRU_RX_ANTNUMBER>

    <NR_CELL_PRU_TRANS_MODE>0</NR_CELL_PRU_TRANS_MODE>

    <NR_CELL_PRU_ORX_ENABLE>0</NR_CELL_PRU_ORX_ENABLE>

    <NR_CELL_PRU_204C_ENABLE>0</NR_CELL_PRU_204C_ENABLE>

    <NR_CELL_PRU_UCPlOG_ENABLE>0</NR_CELL_PRU_UCPlOG_ENABLE>

    <NR_CELL_PA_FREQ>600000</NR_CELL_PA_FREQ>

    <NR_CELL_PA_CHANNEL>0</NR_CELL_PA_CHANNEL>

    <NR_CELL_PA_CHANNEL_ATT1>1</NR_CELL_PA_CHANNEL_ATT1>

    <NR_CELL_PA_CHANNEL_ATT2>1</NR_CELL_PA_CHANNEL_ATT2>

    <NR_CELL_PA_CHANNEL_ATT3>1</NR_CELL_PA_CHANNEL_ATT3>

    <NR_CELL_PA_CHANNEL_ATT4>1</NR_CELL_PA_CHANNEL_ATT4>

  </PRU_CONFIG>

  <SERVED_CELL_PLMN>

    <MAX_NUM_OF_SERVED_CELL_PLMN_INFO>1</MAX_NUM_OF_SERVED_CELL_PLMN_INFO>

    <SERVED_PLMN_0>

      <TAG_MCC_0>0</TAG_MCC_0>

      <TAG_MCC_1>0</TAG_MCC_1>

      <TAG_MCC_2>1</TAG_MCC_2>

      <TAG_MNC_0>0</TAG_MNC_0>

      <TAG_MNC_1>1</TAG_MNC_1>

      <TAG_MNC_2>255</TAG_MNC_2>

    </SERVED_PLMN_0>

    <SERVED_PLMN_1>

      <TAG_MCC_0>0</TAG_MCC_0>

      <TAG_MCC_1>0</TAG_MCC_1>

      <TAG_MCC_2>1</TAG_MCC_2>

      <TAG_MNC_0>0</TAG_MNC_0>

      <TAG_MNC_1>1</TAG_MNC_1>

      <TAG_MNC_2>0</TAG_MNC_2>

    </SERVED_PLMN_1>

    <MAX_NUM_OF_PLMN_SLICE_ENTRY>1</MAX_NUM_OF_PLMN_SLICE_ENTRY>

    <PLMN_SLICE_ENTRY_0>

      <S_NSSAI_SST>1</S_NSSAI_SST>

      <S_NSSAI_SD>1</S_NSSAI_SD>

    </PLMN_SLICE_ENTRY_0>

    <PLMN_SLICE_ENTRY_1>

      <S_NSSAI_SST>2</S_NSSAI_SST>

      <S_NSSAI_SD>2</S_NSSAI_SD>

    </PLMN_SLICE_ENTRY_1>

  </SERVED_CELL_PLMN>

  <COMMON_CFG>

    <SCH_SCS_TYPE>1</SCH_SCS_TYPE>

    <PRACH_CFG_INDX_FR_1>160</PRACH_CFG_INDX_FR_1>

    <PRACH_CFG_INDX_FR_2>81</PRACH_CFG_INDX_FR_2>

    <MSG1_FDM>1</MSG1_FDM>

    <MSG1_FREQ_START>7</MSG1_FREQ_START>

    <PREMBL_REV_TARG_PW>-80</PREMBL_REV_TARG_PW>

    <PWR_RAMPING_STEP>1</PWR_RAMPING_STEP>

    <ZERO_CORRELATION_ZONE_CFG>12</ZERO_CORRELATION_ZONE_CFG>

    <PRACH_ROOT_SEQUENCE_INX>0</PRACH_ROOT_SEQUENCE_INX>

    <SSB_PER_RACH_OCAS_AND_CB_PREMBL_PER_SSB_CHOICE>3</SSB_PER_RACH_OCAS_AND_CB_PREMBL_PER_SSB_CHOICE>

    <RESTRICTED_SET_CFG>0</RESTRICTED_SET_CFG>

  </COMMON_CFG>

  <SCHEDULER_CONFIG>

    <SCH_DED_PREAMBLE_START>47</SCH_DED_PREAMBLE_START>

    <SCH_NO_OF_PREAMBLE>4</SCH_NO_OF_PREAMBLE>

    <SUL_FLAG>false</SUL_FLAG>

    <SUL_CHN_BW>3</SUL_CHN_BW>

    <SUL_SCS_TYPE>0</SUL_SCS_TYPE>

    <DYN_SLOT_FMT_CFG>4</DYN_SLOT_FMT_CFG>

    <SPECIAL_SLOT_FMT_CFG>360693763</SPECIAL_SLOT_FMT_CFG>

    <SCH_SLOT_MUTE_FMT_CFG>0</SCH_SLOT_MUTE_FMT_CFG>

    <SCH_NO_PRBS_MUTE>0</SCH_NO_PRBS_MUTE>

    <SCH_CFI>2</SCH_CFI>

    <CCE_NUM_OF_INTIAL_BWP>32</CCE_NUM_OF_INTIAL_BWP>

    <SCH_DL_MCS>5</SCH_DL_MCS>

    <SCH_UL_MCS>5</SCH_UL_MCS>

    <SCH_DL_UE_PER_TTI>4</SCH_DL_UE_PER_TTI>

    <SCH_UL_UE_PER_TTI>4</SCH_UL_UE_PER_TTI>

    <MAX_MSG3_PER_UL_SLOT>4</MAX_MSG3_PER_UL_SLOT>

    <SCH_SCS_TYPE>1</SCH_SCS_TYPE>

    <SSB_POWER>-24</SSB_POWER>

    <MAX_DL_HARQ_TX>4</MAX_DL_HARQ_TX>

    <MAX_UL_HARQ_TX>4</MAX_UL_HARQ_TX>

    <MAX_MSG4_HARQ_TX>4</MAX_MSG4_HARQ_TX>

    <NUM_CMN_LCS>6</NUM_CMN_LCS>

    <RANK_ADAPT_SWITCH_DL>false</RANK_ADAPT_SWITCH_DL>

    <RANK_ADAPT_SWITCH_UL>false</RANK_ADAPT_SWITCH_UL>

    <AMC_OLLA_SWITCH>true</AMC_OLLA_SWITCH>

    <AMC_ILLA_SWITCH>true</AMC_ILLA_SWITCH>

    <AMC_TARGET_BLER>10</AMC_TARGET_BLER>

    <AMC_ILLA_FILTER_FACTOR>20</AMC_ILLA_FILTER_FACTOR>

    <AMC_ILLA_DL_CQI_SWITCH>false</AMC_ILLA_DL_CQI_SWITCH>

    <AMC_SWITCH>3</AMC_SWITCH>

    <AMC_DL_MAX_MCS>27</AMC_DL_MAX_MCS>

    <AMC_UL_MAX_MCS>27</AMC_UL_MAX_MCS>

    <AMC_OLLA_DOWNSTEP>291</AMC_OLLA_DOWNSTEP>

    <AMC_OLLA_UPSTEP>9</AMC_OLLA_UPSTEP>

    <AMC_ILLA_SNR_UPDATETH>20</AMC_ILLA_SNR_UPDATETH>

    <AMC_SNR_TH>-30</AMC_SNR_TH>

    <AMC_MAXRB_TH>273</AMC_MAXRB_TH>

    <AMC_HARQ_COUNTER>6000</AMC_HARQ_COUNTER>

    <TA_SWITCH>true</TA_SWITCH>

    <TA_FILTER_COEF>5</TA_FILTER_COEF>

    <FSS_SWITCH>false</FSS_SWITCH>

    <FSS_SINR_LOW_TH>7</FSS_SINR_LOW_TH>

    <FSS_SINR_HIGH_TH>17</FSS_SINR_HIGH_TH>

    <FSS_SINR_FILTER_FACTOR>1</FSS_SINR_FILTER_FACTOR>

    <PUCCH_FORMAT_CHOICE>false</PUCCH_FORMAT_CHOICE>

    <PUCCH_FORMAT3_SYM_NUM>4</PUCCH_FORMAT3_SYM_NUM>

    <RLF_TIMER_VALUE>6000</RLF_TIMER_VALUE>

    <SHORT_BSR_VALUE>1750000</SHORT_BSR_VALUE>

    <PDSCH_DMRS_ADDNL_POS>1</PDSCH_DMRS_ADDNL_POS>

    <PUSCH_DMRS_ADDNL_POS>1</PUSCH_DMRS_ADDNL_POS>

    <PDCCH_UCS1_DURATION>1</PDCCH_UCS1_DURATION>

    <DU_SCH_ALGORITHM_SWITCH>0</DU_SCH_ALGORITHM_SWITCH>

    <PDCCH_AGGR_LVL_DFLT>2</PDCCH_AGGR_LVL_DFLT>

    <PDCCH_AGGR_LVL_ADAPTIVE_ADJUSTMENT_CFG>

      <PDCCH_AGGR_LVL_ADAPTIVE_ADJUSTMENT_ENABLED>false</PDCCH_AGGR_LVL_ADAPTIVE_ADJUSTMENT_ENABLED>

      <PDCCH_CQI_FACTOR>5</PDCCH_CQI_FACTOR>

      <PDCCH_CQI_STEP_UP>20</PDCCH_CQI_STEP_UP>

      <PDCCH_CQI_STEP_DOWN>50</PDCCH_CQI_STEP_DOWN>

      <PDCCH_AGGR_LVL_THRESHOLD1>90</PDCCH_AGGR_LVL_THRESHOLD1>

      <PDCCH_AGGR_LVL_THRESHOLD2>70</PDCCH_AGGR_LVL_THRESHOLD2>

      <PDCCH_AGGR_LVL_THRESHOLD4>0</PDCCH_AGGR_LVL_THRESHOLD4>

      <PDCCH_AGGR_LVL_THRESHOLD8>0</PDCCH_AGGR_LVL_THRESHOLD8>

      <PDCCH_AGGR_LVL_THRESHOLD16>0</PDCCH_AGGR_LVL_THRESHOLD16>

    </PDCCH_AGGR_LVL_ADAPTIVE_ADJUSTMENT_CFG>

    <INTER_CELL_INTERFERENCE_COORDINATION_CFG>

      <ICIC_ENABLED>false</ICIC_ENABLED>

      <ICIC_RB_NUM>50</ICIC_RB_NUM>

      <ICIC_RSRP_THRESHOLD_FOR_EDGE_UE>-90</ICIC_RSRP_THRESHOLD_FOR_EDGE_UE>

    </INTER_CELL_INTERFERENCE_COORDINATION_CFG>

    <CELL_UL_POWER_CONTROL_CFG>

      <UL_PUSCH_RSRP_SMOOTH_FACTOR>80</UL_PUSCH_RSRP_SMOOTH_FACTOR>

      <UL_PATHLOSS_SMOOTH_FACTOR>80</UL_PATHLOSS_SMOOTH_FACTOR>

    </CELL_UL_POWER_CONTROL_CFG>

    <CELL_DL_POWER_CONTROL_CFG>

      <DL_PC_SWITCH>0</DL_PC_SWITCH>

      <MAX_TX_POWER>200</MAX_TX_POWER>

      <SS_PBCH_PWR_OFFSET>0</SS_PBCH_PWR_OFFSET>

      <PSS_PWR_OFFSET>1</PSS_PWR_OFFSET>

      <CSIRS_PWR_OFFSET>0</CSIRS_PWR_OFFSET>

      <PDCCH_COM_PWR_OFFSET>0</PDCCH_COM_PWR_OFFSET>

      <PDCCH_PWR_OFFSET>0</PDCCH_PWR_OFFSET>

      <PDSCH_COM_PWR_OFFSET>-300</PDSCH_COM_PWR_OFFSET>

      <PDSCH_PWR_OFFSET>-300</PDSCH_PWR_OFFSET>

      <SSB_TX_NUM>1</SSB_TX_NUM>

    </CELL_DL_POWER_CONTROL_CFG>

  </SCHEDULER_CONFIG>

  <TEST_CONFIG>

    <UL_TPUT_MODE>false</UL_TPUT_MODE>

    <UL_PHR_ENABLE>false</UL_PHR_ENABLE>

    <UL_PRE_SCH>true</UL_PRE_SCH>

    <FORCED_SR>true</FORCED_SR>

    <DL_DUMMY_BO>false</DL_DUMMY_BO>

    <UL_PRE_SCH_PERIOD>0</UL_PRE_SCH_PERIOD>

    <UL_PRE_SCH_DURATION>10240</UL_PRE_SCH_DURATION>

    <DL_SCH_START_PRB>0</DL_SCH_START_PRB>

    <DL_SCH_NUM_PRB>273</DL_SCH_NUM_PRB>

    <DL_SCH_PRB_PER_UE>273</DL_SCH_PRB_PER_UE>

    <UL_SCH_START_PRB>0</UL_SCH_START_PRB>

    <UL_SCH_NUM_PRB>273</UL_SCH_NUM_PRB>

    <UL_SCH_PRB_PER_UE>273</UL_SCH_PRB_PER_UE>

    <UL_PDCCH_PER_SLOT_PER_UE>3</UL_PDCCH_PER_SLOT_PER_UE>

    <SPECIAL_PROCESS_FOR_HW_CPE_PRO1>false</SPECIAL_PROCESS_FOR_HW_CPE_PRO1>

    <UNAUTH_FREQ_CPE_LO_HIGH>false</UNAUTH_FREQ_CPE_LO_HIGH>

    <MSG4_TEST_MODE>true</MSG4_TEST_MODE>

    <REEST_TRIGGER_FOR_TEST>false</REEST_TRIGGER_FOR_TEST>

    <STE_ENABLE>false</STE_ENABLE>

    <DL_DELTA>3</DL_DELTA>

    <DULOG_FILENUM>5</DULOG_FILENUM>

    <SIB1_STUB_ENABLE>false</SIB1_STUB_ENABLE>

    <SIB1_STUB_PERIOD>640</SIB1_STUB_PERIOD>

    <SIB1_STUB_BAND>125</SIB1_STUB_BAND>

    <SPEC_C_RNTI>0</SPEC_C_RNTI>

    <SPEC_UE_UL_RB_NUM>4</SPEC_UE_UL_RB_NUM>

    <SPEC_UE_DL_RB_NUM>1</SPEC_UE_DL_RB_NUM>

  </TEST_CONFIG>

  <INITIAL_BWP>

    <BWP_CP_TYPE>true</BWP_CP_TYPE>

    <INITIAL_BWP_PUSCH_COMMON>

      <P_0_NOMINAL>-70</P_0_NOMINAL>

      <MSG3_DELTA_PREMBL>0</MSG3_DELTA_PREMBL>

      <P_0_NOMINAL_WITH_GRANT>-70</P_0_NOMINAL_WITH_GRANT>

      <MSG3_ALPHA>7</MSG3_ALPHA>

      <PUSCH_ALPHA>7</PUSCH_ALPHA>

      <UCI_ON_PUSCH_SCALING>3</UCI_ON_PUSCH_SCALING>

    </INITIAL_BWP_PUSCH_COMMON>

  </INITIAL_BWP>

  <FREQUENCY_CONFIG_DL>

    <NR_FREQ_BAND>41</NR_FREQ_BAND>

    <NR_DL_CENTER_FREQ>2566170</NR_DL_CENTER_FREQ>

    <NR_DL_ABS_FREQ_POINT_A>2517030</NR_DL_ABS_FREQ_POINT_A>

    <NR_DL_ABS_ARFCN_POINT_A>505092</NR_DL_ABS_ARFCN_POINT_A>

    <NR_DL_ABS_FREQ_POINT_SSB>2524950</NR_DL_ABS_FREQ_POINT_SSB>

    <NR_DL_ABS_ARFCN_POINT_SSB>506910</NR_DL_ABS_ARFCN_POINT_SSB>

    <NR_DL_EARFCN>514920</NR_DL_EARFCN>

  </FREQUENCY_CONFIG_DL>

  <FREQUENCY_CONFIG_UL>

    <NR_FREQ_BAND>41</NR_FREQ_BAND>

    <NR_UL_CENTER_FREQ>2566170</NR_UL_CENTER_FREQ>

    <NR_UL_ABS_FREQ_POINT_A>2517030</NR_UL_ABS_FREQ_POINT_A>

    <NR_UL_ABS_ARFCN_POINT_A>505092</NR_UL_ABS_ARFCN_POINT_A>

    <NR_UL_EARFCN>514920</NR_UL_EARFCN>

    <P_MAX>23</P_MAX>

  </FREQUENCY_CONFIG_UL>

  <SLICE>

    <MAX_NUM_OF_SLICE_ENTRY>3</MAX_NUM_OF_SLICE_ENTRY>

    <SLICE_ENTRY_0>

      <S_NSI_ID>1</S_NSI_ID>

      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>

      <S_DL_PRB>11</S_DL_PRB>

      <S_UL_PRB>11</S_UL_PRB>

      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>

      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>

    </SLICE_ENTRY_0>

    <SLICE_ENTRY_1>

      <S_NSI_ID>2</S_NSI_ID>

      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>

      <S_DL_PRB>22</S_DL_PRB>

      <S_UL_PRB>22</S_UL_PRB>

      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>

      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>

    </SLICE_ENTRY_1>

    <SLICE_ENTRY_2>

      <S_NSI_ID>3</S_NSI_ID>

      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>

      <S_DL_PRB>11</S_DL_PRB>

      <S_UL_PRB>11</S_UL_PRB>

      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>

      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>

    </SLICE_ENTRY_2>

    <MAX_NUM_NS_RES_CFG_ENTRY>2</MAX_NUM_NS_RES_CFG_ENTRY>

    <NS_RES_CFG_ENTRY_0>

      <NS_DL_PRB>44</NS_DL_PRB>

      <NS_UL_PRB>44</NS_UL_PRB>

    </NS_RES_CFG_ENTRY_0>

    <NS_RES_CFG_ENTRY_1>

      <NS_DL_PRB>22</NS_DL_PRB>

      <NS_UL_PRB>22</NS_UL_PRB>

    </NS_RES_CFG_ENTRY_1>

  </SLICE>

  <L1_INFO>

    <TAC>1</TAC>

  </L1_INFO>

  <M-BWP>

    <MAX_NUM_OF_UL_BWP>1</MAX_NUM_OF_UL_BWP>

    <MAX_NUM_OF_DL_BWP>1</MAX_NUM_OF_DL_BWP>

    <DL_BWP_ENTRY_0>

      <DL_BWP_ID>0</DL_BWP_ID>

      <DL_BWP_SCS>1</DL_BWP_SCS>

      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>

      <DL_BWP_START_RB>0</DL_BWP_START_RB>

      <DL_BWP_MAX_RB>273</DL_BWP_MAX_RB>

      <AVG_AGG_LVL>2</AVG_AGG_LVL>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

    </DL_BWP_ENTRY_0>

    <DL_BWP_ENTRY_1>

      <DL_BWP_ID>1</DL_BWP_ID>

      <DL_BWP_SCS>1</DL_BWP_SCS>

      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>

      <DL_BWP_START_RB>0</DL_BWP_START_RB>

      <DL_BWP_MAX_RB>100</DL_BWP_MAX_RB>

      <AVG_AGG_LVL>2</AVG_AGG_LVL>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

    </DL_BWP_ENTRY_1>

    <DL_BWP_ENTRY_2>

      <DL_BWP_ID>2</DL_BWP_ID>

      <DL_BWP_SCS>1</DL_BWP_SCS>

      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>

      <DL_BWP_START_RB>100</DL_BWP_START_RB>

      <DL_BWP_MAX_RB>173</DL_BWP_MAX_RB>

      <AVG_AGG_LVL>2</AVG_AGG_LVL>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

    </DL_BWP_ENTRY_2>

    <DL_BWP_ENTRY_3>

      <DL_BWP_ID>3</DL_BWP_ID>

      <DL_BWP_SCS>1</DL_BWP_SCS>

      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>

      <DL_BWP_START_RB>42</DL_BWP_START_RB>

      <DL_BWP_MAX_RB>14</DL_BWP_MAX_RB>

    </DL_BWP_ENTRY_3>

    <DL_BWP_ENTRY_4>

      <DL_BWP_ID>4</DL_BWP_ID>

      <DL_BWP_SCS>1</DL_BWP_SCS>

      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>

      <DL_BWP_START_RB>0</DL_BWP_START_RB>

      <DL_BWP_MAX_RB>14</DL_BWP_MAX_RB>

    </DL_BWP_ENTRY_4>

    <UL_BWP_ENTRY_0>

      <UL_BWP_ID>0</UL_BWP_ID>

      <UL_BWP_SCS>1</UL_BWP_SCS>

      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>

      <UL_BWP_START_RB>0</UL_BWP_START_RB>

      <UL_BWP_MAX_RB>273</UL_BWP_MAX_RB>

      <SR_PRDCTY>40</SR_PRDCTY>

      <MAX_PAYLOAD_LEN1_F2>8</MAX_PAYLOAD_LEN1_F2>

      <MAX_PAYLOAD_LEN2_F2>12</MAX_PAYLOAD_LEN2_F2>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>

      <CONFIG_PARAM_NUM_SRS_SYM>1</CONFIG_PARAM_NUM_SRS_SYM>

      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>

      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>12</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>

      <CONFIG_PARAM_NUM_SRS_USAGE>0</CONFIG_PARAM_NUM_SRS_USAGE>

      <CONFIG_PARAM_NUM_SRS_NROFSYMBOLS>1</CONFIG_PARAM_NUM_SRS_NROFSYMBOLS>

      <CONFIG_PARAM_NUM_SRS_REPETITIONFACTOR>1</CONFIG_PARAM_NUM_SRS_REPETITIONFACTOR>

      <CONFIG_PARAM_NUM_SRS_FREQHOPCFG>1</CONFIG_PARAM_NUM_SRS_FREQHOPCFG>

      <CONFIG_PARAM_NUM_SRS_CSRS>54</CONFIG_PARAM_NUM_SRS_CSRS>

      <CONFIG_PARAM_NUM_SRS_BSRS>2</CONFIG_PARAM_NUM_SRS_BSRS>

      <CONFIG_PARAM_NUM_SRS_BHOP>0</CONFIG_PARAM_NUM_SRS_BHOP>

      <CONFIG_PARAM_NUM_SRS_PERIOD>80</CONFIG_PARAM_NUM_SRS_PERIOD>

      <CONFIG_PARAM_NUM_SRS_SLOT_GAP>20</CONFIG_PARAM_NUM_SRS_SLOT_GAP>

      <CONFIG_PARAM_NUM_SRS_ALPHA>7</CONFIG_PARAM_NUM_SRS_ALPHA>

      <CONFIG_PARAM_NUM_SRS_P0>-70</CONFIG_PARAM_NUM_SRS_P0>

    </UL_BWP_ENTRY_0>

    <UL_BWP_ENTRY_1>

      <UL_BWP_ID>1</UL_BWP_ID>

      <UL_BWP_SCS>1</UL_BWP_SCS>

      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>

      <UL_BWP_START_RB>0</UL_BWP_START_RB>

      <UL_BWP_MAX_RB>100</UL_BWP_MAX_RB>

      <SR_PRDCTY>40</SR_PRDCTY>

      <MAX_PAYLOAD_LEN1_F2>24</MAX_PAYLOAD_LEN1_F2>

      <MAX_PAYLOAD_LEN2_F2>36</MAX_PAYLOAD_LEN2_F2>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>

      <CONFIG_PARAM_NUM_SRS_SYM>0</CONFIG_PARAM_NUM_SRS_SYM>

      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>

      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>1</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>

    </UL_BWP_ENTRY_1>

    <UL_BWP_ENTRY_2>

      <UL_BWP_ID>2</UL_BWP_ID>

      <UL_BWP_SCS>1</UL_BWP_SCS>

      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>

      <UL_BWP_START_RB>100</UL_BWP_START_RB>

      <UL_BWP_MAX_RB>173</UL_BWP_MAX_RB>

      <SR_PRDCTY>40</SR_PRDCTY>

      <MAX_PAYLOAD_LEN1_F2>24</MAX_PAYLOAD_LEN1_F2>

      <MAX_PAYLOAD_LEN2_F2>36</MAX_PAYLOAD_LEN2_F2>

      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>

      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>

      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>

      <CONFIG_PARAM_NUM_SRS_SYM>0</CONFIG_PARAM_NUM_SRS_SYM>

      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>

      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>1</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>

    </UL_BWP_ENTRY_2>

    <UL_BWP_ENTRY_3>

      <UL_BWP_ID>3</UL_BWP_ID>

      <UL_BWP_SCS>1</UL_BWP_SCS>

      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>

      <UL_BWP_START_RB>42</UL_BWP_START_RB>

      <UL_BWP_MAX_RB>14</UL_BWP_MAX_RB>

    </UL_BWP_ENTRY_3>

    <UL_BWP_ENTRY_4>

      <UL_BWP_ID>4</UL_BWP_ID>

      <UL_BWP_SCS>1</UL_BWP_SCS>

      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>

      <UL_BWP_START_RB>0</UL_BWP_START_RB>

      <UL_BWP_MAX_RB>14</UL_BWP_MAX_RB>

    </UL_BWP_ENTRY_4>

  </M-BWP>

  <PCCH_CONFIG>

    <PAGING_CYCLE>1</PAGING_CYCLE>

  </PCCH_CONFIG>

  <PFS_CONFIG>

    <NR_5QI_COEFFICIENT>5</NR_5QI_COEFFICIENT>

    <GBR_SERVED_RATE_COEFFICIENT>5</GBR_SERVED_RATE_COEFFICIENT>

    <UE_PFS_COEFFICIENT>5</UE_PFS_COEFFICIENT>

    <THROUGHPUT_COEFFICIENT>5</THROUGHPUT_COEFFICIENT>

    <FAIRNESS_COEFFICIENT>5</FAIRNESS_COEFFICIENT>

  </PFS_CONFIG>

  <PDSCH_RATE_MATCHING>

    <RATE_MATCH_SS_PBCH_ENABLED>false</RATE_MATCH_SS_PBCH_ENABLED>

    <RATE_MATCH_CORESET_ENABLED>false</RATE_MATCH_CORESET_ENABLED>

  </PDSCH_RATE_MATCHING>

  <CYCLIC_SHIFT>

    <CYCLIC_SHIFT_INFO>{0}</CYCLIC_SHIFT_INFO>

  </CYCLIC_SHIFT>

  <CSI_CFG>

    <NZP_CSIRS_PERIOD>40</NZP_CSIRS_PERIOD>

    <NZP_CSIRS_DENSITY>1</NZP_CSIRS_DENSITY>

    <NZP_CSIRS_FIRST_SYM_TIME_DOMIN>13</NZP_CSIRS_FIRST_SYM_TIME_DOMIN>

    <NZP_CSIRS_CDM_TYPE>2</NZP_CSIRS_CDM_TYPE>

    <NZP_CSIRS_START_RB>0</NZP_CSIRS_START_RB>

    <NZP_CSIRS_RB_NUM>272</NZP_CSIRS_RB_NUM>

    <CSI_PRDCTY>160</CSI_PRDCTY>

  </CSI_CFG>

  <GAP_MEASUREMENT>

    <GAP_PATTERN_ID>5</GAP_PATTERN_ID>

  </GAP_MEASUREMENT>

</DU-CELL>