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# ##########################################################
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# General System Level Configuation File
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# Core Configuration for DU
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[SYS_CPU_CORE_CONFIG]
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TTI_TIMER_COREID = 7
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LOWER_CL_COREID = 7
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CL_RECV_COREID = 6
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DUAPP_LOG_COREID = 7
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DBG_LOG_COREID = 7
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WIRESHARK_LOG_COREID = 7
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CLI_AGENT_COREID = 7
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OAM_AGENT_COREID = 7
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UDP_RX_COREID = 7
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SCTP_COREID = 7
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WKR_COREID = {4,5}
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# Core Configuration for DU Support URLLC
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[SYS_CPU_CORE_CONFIG_URLLC]
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TTI_TIMER_COREID = 7
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LOWER_CL_COREID = 7
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WIRESHARK_LOG_COREID = 7
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UDP_RX_COREID = 7
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CLI_AGENT_COREID = 7
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OAM_AGENT_COREID = 7
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CL_RECV_COREID = 6
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SCTP_COREID = 7
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URLLC_UDP_RX_COREID = 5
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URLLC_CL_RECV_COREID = 7
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URLLC_WKR_COREID = {4,5}
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WKR_COREID = {4,5}
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DUAPP_LOG_COREID = 7
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DBG_LOG_COREID = 7
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# Number of Eth Ports determine how many eth ports are
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# used in the system.
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# Based on this configuration Eth ports are configured
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[SYS_EAL_CONFIG]
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HUGE_PAGE_CONFIG_FILE = gnb_du_rte_config
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HUGE_PAGE_SIZE = 1024
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NUM_THREADS_PER_CORE = 1
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NUM_LCORE = 4
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NUM_ETH_PORT = 2
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FRONTHAUL_EN = 1
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[CORE_0]
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CORE_ID = 4
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[CORE_1]
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CORE_ID = 5
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[CORE_2]
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CORE_ID = 6
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[CORE_3]
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CORE_ID = 7
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# CONFIG_0, Whitelist PCI Address for Fronthaul
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[ETH_PORT_CONFIG_0]
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PCI_ADDRESS = 0000:19:00.0
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D_ETH_ADDRESS = 00:00:00:00:00:00
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NUM_OF_TX_Q_PER_PORT = 1
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NUM_OF_RX_Q_PER_PORT = 1
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NUM_RX_DESC = 128
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NUM_TX_DESC = 512
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MAX_PAYLOAD_SIZE = 9728
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# CONFIG_1, Whitelist PCI Address for TX Backhaul
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[ETH_PORT_CONFIG_1]
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PCI_ADDRESS = 0000:19:00.1
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D_ETH_ADDRESS = 00:00:00:00:00:01
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NUM_OF_TX_Q_PER_PORT = 1
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NUM_OF_RX_Q_PER_PORT = 1
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NUM_RX_DESC = 128
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NUM_TX_DESC = 512
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MAX_PAYLOAD_SIZE = 9728
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# CONFIG_2, Whitelist PCI Address for RX Backhaul
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# If RX and TX for Backhaul are using different ports.
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# To configure this update the NUM_ETH_PORT param to 3.
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#
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[ETH_PORT_CONFIG_2]
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PCI_ADDRESS = 0000:19:00.1
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D_ETH_ADDRESS = 00:00:00:00:00:01
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NUM_OF_TX_Q_PER_PORT = 1
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NUM_OF_RX_Q_PER_PORT = 1
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NUM_RX_DESC = 128
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NUM_TX_DESC = 512
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MAX_PAYLOAD_SIZE = 9728
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# ##########################################################
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# N/W Protocol Configuration for DU
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[SYS_NET_CONFIG]
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ETH_PROTO_TYPE = IPv4
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IP_SRC_ADDRESS = 10.10.10.1
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IP_DST_ADDRESS = 10.10.10.2
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IP_PROTO_TYPE = UDP
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UDP_SRC_PORT = 2152
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UDP_DST_PORT = 2152
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# ##########################################################
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[SCH_TASK_INFO]
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SCH_LVL1_TSK_GROUP_INFO = {1}
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SCH_LVL2_TSK_GROUP_INFO = {1}
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[SCH_TASK_INFO_URLLC]
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SCH_LVL1_TSK_GROUP_INFO = {1},{17}
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SCH_LVL2_TSK_GROUP_INFO = {1},{17}
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# #########################################################
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# #24~31bitsCOMMON##
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# #24:du common 25:du app
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# #
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# #16~23bis YS-CL##
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# #16:ys dl 17:ys ul 18:ys pucch 19:ys common 20:ys TTI
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# #
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# #8~15bits RLC##
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# #8:rlc am 9:rlc um 10:rlc tm 11:ue config 12:cell config 13:rlc common
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# #
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# #0~7bits MAC##
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# #0:random access 1:dl sch 2:ul sch 3:resource allocate 4:ue config 5:cell config 6:mac common 7:ul and dl amc
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# # LEVEL: 1 Trace; 2 Info; 3 Debug; 4 Warnning; 5 Error; 6 Fatal
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[ZLOG_CONFIG]
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ZLOG_MASK = 0x0203ff6f
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ZLOG_LEVEL = 5
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# #########################################################
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# params for task trace logging:
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#
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# TASK_TRACE_ENTITY_MASK: indicates enable or disable task trace for a entity
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# 0 bit: ENTITY_UNUSED
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# 1 bit: SS_RLC_DL_CMN
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# 2 bit: SS_RLC_UL_CMN
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# 3 bit: SS_RLC_DL_UE
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# 4 bit: SS_RLC_DL_UE_DUP
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# 5 bit: SS_RLC_UL_UE
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# 6 bit: SS_MAC_UE
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# 7 bit: SS_CMN_TMR
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# 8 bit: SS_SCH_LVL1_CMN
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# 9 bit: SS_SCH_LVL2_CMN
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# 10 bit: SS_CL_CMN
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# ......
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# refer to cmn_event.h for more definition
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#
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# TASK_TRACE_FLUSH_INTERVAL: interval to flush log, unit: microseconds
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#
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# TASK_TRACE_HIS_LENGTH: history buffer length for logging before each log flush
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#
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# DU SHM SWITCH
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[F1U_SHM_CONFIG]
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F1U_SHM_SWITCH = 1
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F1U_SHM_NOTIFY_INTERVAL = 50
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[TASK_TRACE_CONFIG]
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# trace disabled by default
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TASK_TRACE_ENTITY_MASK = 0
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TASK_TRACE_FLUSH_INTERVAL = 100
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TASK_TRACE_HIS_LENGTH = 100
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# #########################################################
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# Parameters for system test
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[SYS_TEST_CONFIG]
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PUCCH_PUSCH_SPLIT = 0
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STE_ENABLE = 0
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CPE_5800_LO = 2200000
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CPE_600_LO = 3038000
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PHY_STARTFAIL = 0
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E500_SCRAMBLEID_ENABLE = 0
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UP_TOOL_ENABLE = 0
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