|
1
|
<GNB-CU-DULIST xmlns="http://www.yunzhiruantong.com/yzrt/yzmm/gnb/cu/dulist">
|
|
2
|
<DU_LIST_0>
|
|
3
|
<DU_ID>1</DU_ID>
|
|
4
|
<GNB_SCTP_IP_ADDRESS>192.168.68.242</GNB_SCTP_IP_ADDRESS>
|
|
5
|
<SERVED_CELL_LIST>{0}</SERVED_CELL_LIST>
|
|
6
|
<CELL_CFG_0>
|
|
7
|
<DU_ID>1</DU_ID>
|
|
8
|
<NR_PCI>242</NR_PCI>
|
|
9
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
10
|
<TAG_MCC_0>0</TAG_MCC_0>
|
|
11
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
12
|
<TAG_MCC_2>1</TAG_MCC_2>
|
|
13
|
<TAG_MNC_0>0</TAG_MNC_0>
|
|
14
|
<TAG_MNC_1>1</TAG_MNC_1>
|
|
15
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
16
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
17
|
<NUM_EUTRA_NEIGHBOUR_CELLS>0</NUM_EUTRA_NEIGHBOUR_CELLS>
|
|
18
|
<NUM_NR_NEIGHBOUR_CELLS>0</NUM_NR_NEIGHBOUR_CELLS>
|
|
19
|
<EUTRA_NEIGHBOUR_0>
|
|
20
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
21
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
22
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
23
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
24
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
25
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
26
|
<ENODEB_ID_TYPE>HOME_ENB_ID</ENODEB_ID_TYPE>
|
|
27
|
<ENODEB_ID>1</ENODEB_ID>
|
|
28
|
<EUTRA_CELL_ID>2</EUTRA_CELL_ID>
|
|
29
|
</EUTRA_NEIGHBOUR_0>
|
|
30
|
<NR_NEIGHBOUR_0>
|
|
31
|
<NR_PCI>40</NR_PCI>
|
|
32
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
33
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
34
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
35
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
36
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
37
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
38
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
39
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
40
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
41
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
42
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
43
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
44
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
45
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
46
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
47
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
48
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
49
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
50
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
51
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
52
|
</NR_NEIGHBOUR_0>
|
|
53
|
<NR_NEIGHBOUR_1>
|
|
54
|
<NR_PCI>50</NR_PCI>
|
|
55
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
56
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
57
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
58
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
59
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
60
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
61
|
<NR_GNB_ID>50</NR_GNB_ID>
|
|
62
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
63
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
64
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
65
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
66
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
67
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
68
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
69
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
70
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
71
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
72
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
73
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
74
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
75
|
</NR_NEIGHBOUR_1>
|
|
76
|
<NR_NEIGHBOUR_2>
|
|
77
|
<NR_PCI>60</NR_PCI>
|
|
78
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
79
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
80
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
81
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
82
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
83
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
84
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
85
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
86
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
87
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
88
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
89
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
90
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
91
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
92
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
93
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
94
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
95
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
96
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
97
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
98
|
</NR_NEIGHBOUR_2>
|
|
99
|
<NR_NEIGHBOUR_3>
|
|
100
|
<NR_PCI>60</NR_PCI>
|
|
101
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
102
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
103
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
104
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
105
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
106
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
107
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
108
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
109
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
110
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
111
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
112
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
113
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
114
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
115
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
116
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
117
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
118
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
119
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
120
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
121
|
</NR_NEIGHBOUR_3>
|
|
122
|
<NR_NEIGHBOUR_4>
|
|
123
|
<NR_PCI>60</NR_PCI>
|
|
124
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
125
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
126
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
127
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
128
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
129
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
130
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
131
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
132
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
133
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
134
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
135
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
136
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
137
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
138
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
139
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
140
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
141
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
142
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
143
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
144
|
</NR_NEIGHBOUR_4>
|
|
145
|
<NR_NEIGHBOUR_5>
|
|
146
|
<NR_PCI>60</NR_PCI>
|
|
147
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
148
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
149
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
150
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
151
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
152
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
153
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
154
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
155
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
156
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
157
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
158
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
159
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
160
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
161
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
162
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
163
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
164
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
165
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
166
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
167
|
</NR_NEIGHBOUR_5>
|
|
168
|
<NR_NEIGHBOUR_6>
|
|
169
|
<NR_PCI>60</NR_PCI>
|
|
170
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
171
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
172
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
173
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
174
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
175
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
176
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
177
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
178
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
179
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
180
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
181
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
182
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
183
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
184
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
185
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
186
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
187
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
188
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
189
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
190
|
</NR_NEIGHBOUR_6>
|
|
191
|
<NR_NEIGHBOUR_7>
|
|
192
|
<NR_PCI>60</NR_PCI>
|
|
193
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
194
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
195
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
196
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
197
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
198
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
199
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
200
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
201
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
202
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
203
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
204
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
205
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
206
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
207
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
208
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
209
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
210
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
211
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
212
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
213
|
</NR_NEIGHBOUR_7>
|
|
214
|
<NR_NEIGHBOUR_8>
|
|
215
|
<NR_PCI>60</NR_PCI>
|
|
216
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
217
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
218
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
219
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
220
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
221
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
222
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
223
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
224
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
225
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
226
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
227
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
228
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
229
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
230
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
231
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
232
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
233
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
234
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
235
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
236
|
</NR_NEIGHBOUR_8>
|
|
237
|
<NR_NEIGHBOUR_9>
|
|
238
|
<NR_PCI>60</NR_PCI>
|
|
239
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
240
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
241
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
242
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
243
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
244
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
245
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
246
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
247
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
248
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
249
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
250
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
251
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
252
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
253
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
254
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
255
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
256
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
257
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
258
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
259
|
</NR_NEIGHBOUR_9>
|
|
260
|
<NR_NEIGHBOUR_10>
|
|
261
|
<NR_PCI>60</NR_PCI>
|
|
262
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
263
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
264
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
265
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
266
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
267
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
268
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
269
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
270
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
271
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
272
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
273
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
274
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
275
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
276
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
277
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
278
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
279
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
280
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
281
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
282
|
</NR_NEIGHBOUR_10>
|
|
283
|
<NR_NEIGHBOUR_11>
|
|
284
|
<NR_PCI>60</NR_PCI>
|
|
285
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
286
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
287
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
288
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
289
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
290
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
291
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
292
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
293
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
294
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
295
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
296
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
297
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
298
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
299
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
300
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
301
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
302
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
303
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
304
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
305
|
</NR_NEIGHBOUR_11>
|
|
306
|
<NR_NEIGHBOUR_12>
|
|
307
|
<NR_PCI>60</NR_PCI>
|
|
308
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
309
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
310
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
311
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
312
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
313
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
314
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
315
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
316
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
317
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
318
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
319
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
320
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
321
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
322
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
323
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
324
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
325
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
326
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
327
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
328
|
</NR_NEIGHBOUR_12>
|
|
329
|
<NR_NEIGHBOUR_13>
|
|
330
|
<NR_PCI>60</NR_PCI>
|
|
331
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
332
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
333
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
334
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
335
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
336
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
337
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
338
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
339
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
340
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
341
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
342
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
343
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
344
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
345
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
346
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
347
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
348
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
349
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
350
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
351
|
</NR_NEIGHBOUR_13>
|
|
352
|
<NR_NEIGHBOUR_14>
|
|
353
|
<NR_PCI>60</NR_PCI>
|
|
354
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
355
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
356
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
357
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
358
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
359
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
360
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
361
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
362
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
363
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
364
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
365
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
366
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
367
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
368
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
369
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
370
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
371
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
372
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
373
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
374
|
</NR_NEIGHBOUR_14>
|
|
375
|
<NR_NEIGHBOUR_15>
|
|
376
|
<NR_PCI>60</NR_PCI>
|
|
377
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
378
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
379
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
380
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
381
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
382
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
383
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
384
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
385
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
386
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
387
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
388
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
389
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
390
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
391
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
392
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
393
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
394
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
395
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
396
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
397
|
</NR_NEIGHBOUR_15>
|
|
398
|
<NR_NEIGHBOUR_16>
|
|
399
|
<NR_PCI>60</NR_PCI>
|
|
400
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
401
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
402
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
403
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
404
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
405
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
406
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
407
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
408
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
409
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
410
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
411
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
412
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
413
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
414
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
415
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
416
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
417
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
418
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
419
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
420
|
</NR_NEIGHBOUR_16>
|
|
421
|
<NR_NEIGHBOUR_17>
|
|
422
|
<NR_PCI>60</NR_PCI>
|
|
423
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
424
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
425
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
426
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
427
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
428
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
429
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
430
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
431
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
432
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
433
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
434
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
435
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
436
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
437
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
438
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
439
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
440
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
441
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
442
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
443
|
</NR_NEIGHBOUR_17>
|
|
444
|
<NR_NEIGHBOUR_18>
|
|
445
|
<NR_PCI>60</NR_PCI>
|
|
446
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
447
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
448
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
449
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
450
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
451
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
452
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
453
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
454
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
455
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
456
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
457
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
458
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
459
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
460
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
461
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
462
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
463
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
464
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
465
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
466
|
</NR_NEIGHBOUR_18>
|
|
467
|
<NR_NEIGHBOUR_19>
|
|
468
|
<NR_PCI>60</NR_PCI>
|
|
469
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
470
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
471
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
472
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
473
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
474
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
475
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
476
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
477
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
478
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
479
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
480
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
481
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
482
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
483
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
484
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
485
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
486
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
487
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
488
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
489
|
</NR_NEIGHBOUR_19>
|
|
490
|
<NR_NEIGHBOUR_20>
|
|
491
|
<NR_PCI>60</NR_PCI>
|
|
492
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
493
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
494
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
495
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
496
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
497
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
498
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
499
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
500
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
501
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
502
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
503
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
504
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
505
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
506
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
507
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
508
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
509
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
510
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
511
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
512
|
</NR_NEIGHBOUR_20>
|
|
513
|
<NR_NEIGHBOUR_21>
|
|
514
|
<NR_PCI>60</NR_PCI>
|
|
515
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
516
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
517
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
518
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
519
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
520
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
521
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
522
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
523
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
524
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
525
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
526
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
527
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
528
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
529
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
530
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
531
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
532
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
533
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
534
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
535
|
</NR_NEIGHBOUR_21>
|
|
536
|
<NR_NEIGHBOUR_22>
|
|
537
|
<NR_PCI>60</NR_PCI>
|
|
538
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
539
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
540
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
541
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
542
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
543
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
544
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
545
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
546
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
547
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
548
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
549
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
550
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
551
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
552
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
553
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
554
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
555
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
556
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
557
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
558
|
</NR_NEIGHBOUR_22>
|
|
559
|
<NR_NEIGHBOUR_23>
|
|
560
|
<NR_PCI>60</NR_PCI>
|
|
561
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
562
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
563
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
564
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
565
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
566
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
567
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
568
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
569
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
570
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
571
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
572
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
573
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
574
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
575
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
576
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
577
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
578
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
579
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
580
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
581
|
</NR_NEIGHBOUR_23>
|
|
582
|
<NR_NEIGHBOUR_24>
|
|
583
|
<NR_PCI>60</NR_PCI>
|
|
584
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
585
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
586
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
587
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
588
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
589
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
590
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
591
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
592
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
593
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
594
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
595
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
596
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
597
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
598
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
599
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
600
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
601
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
602
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
603
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
604
|
</NR_NEIGHBOUR_24>
|
|
605
|
<NR_NEIGHBOUR_25>
|
|
606
|
<NR_PCI>60</NR_PCI>
|
|
607
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
608
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
609
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
610
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
611
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
612
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
613
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
614
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
615
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
616
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
617
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
618
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
619
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
620
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
621
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
622
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
623
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
624
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
625
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
626
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
627
|
</NR_NEIGHBOUR_25>
|
|
628
|
<NR_NEIGHBOUR_26>
|
|
629
|
<NR_PCI>60</NR_PCI>
|
|
630
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
631
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
632
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
633
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
634
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
635
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
636
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
637
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
638
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
639
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
640
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
641
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
642
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
643
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
644
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
645
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
646
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
647
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
648
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
649
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
650
|
</NR_NEIGHBOUR_26>
|
|
651
|
<NR_NEIGHBOUR_27>
|
|
652
|
<NR_PCI>60</NR_PCI>
|
|
653
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
654
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
655
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
656
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
657
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
658
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
659
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
660
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
661
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
662
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
663
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
664
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
665
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
666
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
667
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
668
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
669
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
670
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
671
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
672
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
673
|
</NR_NEIGHBOUR_27>
|
|
674
|
<NR_NEIGHBOUR_28>
|
|
675
|
<NR_PCI>60</NR_PCI>
|
|
676
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
677
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
678
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
679
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
680
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
681
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
682
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
683
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
684
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
685
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
686
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
687
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
688
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
689
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
690
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
691
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
692
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
693
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
694
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
695
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
696
|
</NR_NEIGHBOUR_28>
|
|
697
|
<NR_NEIGHBOUR_29>
|
|
698
|
<NR_PCI>60</NR_PCI>
|
|
699
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
700
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
701
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
702
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
703
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
704
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
705
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
706
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
707
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
708
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
709
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
710
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
711
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
712
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
713
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
714
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
715
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
716
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
717
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
718
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
719
|
</NR_NEIGHBOUR_29>
|
|
720
|
<NR_NEIGHBOUR_30>
|
|
721
|
<NR_PCI>60</NR_PCI>
|
|
722
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
723
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
724
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
725
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
726
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
727
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
728
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
729
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
730
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
731
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
732
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
733
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
734
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
735
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
736
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
737
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
738
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
739
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
740
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
741
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
742
|
</NR_NEIGHBOUR_30>
|
|
743
|
<NR_NEIGHBOUR_31>
|
|
744
|
<NR_PCI>60</NR_PCI>
|
|
745
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
746
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
747
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
748
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
749
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
750
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
751
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
752
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
753
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
754
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
755
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
756
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
757
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
758
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
759
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
760
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
761
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
762
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
763
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
764
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
765
|
</NR_NEIGHBOUR_31>
|
|
766
|
<NR_NEIGHBOUR_32>
|
|
767
|
<NR_PCI>60</NR_PCI>
|
|
768
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
769
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
770
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
771
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
772
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
773
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
774
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
775
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
776
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
777
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
778
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
779
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
780
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
781
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
782
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
783
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
784
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
785
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
786
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
787
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
788
|
</NR_NEIGHBOUR_32>
|
|
789
|
<NR_NEIGHBOUR_33>
|
|
790
|
<NR_PCI>60</NR_PCI>
|
|
791
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
792
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
793
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
794
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
795
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
796
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
797
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
798
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
799
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
800
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
801
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
802
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
803
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
804
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
805
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
806
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
807
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
808
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
809
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
810
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
811
|
</NR_NEIGHBOUR_33>
|
|
812
|
<NR_NEIGHBOUR_34>
|
|
813
|
<NR_PCI>60</NR_PCI>
|
|
814
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
815
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
816
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
817
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
818
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
819
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
820
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
821
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
822
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
823
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
824
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
825
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
826
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
827
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
828
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
829
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
830
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
831
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
832
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
833
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
834
|
</NR_NEIGHBOUR_34>
|
|
835
|
<NR_NEIGHBOUR_35>
|
|
836
|
<NR_PCI>60</NR_PCI>
|
|
837
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
838
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
839
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
840
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
841
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
842
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
843
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
844
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
845
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
846
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
847
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
848
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
849
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
850
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
851
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
852
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
853
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
854
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
855
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
856
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
857
|
</NR_NEIGHBOUR_35>
|
|
858
|
<NR_NEIGHBOUR_36>
|
|
859
|
<NR_PCI>60</NR_PCI>
|
|
860
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
861
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
862
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
863
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
864
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
865
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
866
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
867
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
868
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
869
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
870
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
871
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
872
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
873
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
874
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
875
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
876
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
877
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
878
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
879
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
880
|
</NR_NEIGHBOUR_36>
|
|
881
|
<NR_NEIGHBOUR_37>
|
|
882
|
<NR_PCI>60</NR_PCI>
|
|
883
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
884
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
885
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
886
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
887
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
888
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
889
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
890
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
891
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
892
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
893
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
894
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
895
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
896
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
897
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
898
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
899
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
900
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
901
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
902
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
903
|
</NR_NEIGHBOUR_37>
|
|
904
|
<NR_NEIGHBOUR_38>
|
|
905
|
<NR_PCI>60</NR_PCI>
|
|
906
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
907
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
908
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
909
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
910
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
911
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
912
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
913
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
914
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
915
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
916
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
917
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
918
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
919
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
920
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
921
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
922
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
923
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
924
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
925
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
926
|
</NR_NEIGHBOUR_38>
|
|
927
|
<NR_NEIGHBOUR_39>
|
|
928
|
<NR_PCI>60</NR_PCI>
|
|
929
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
930
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
931
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
932
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
933
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
934
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
935
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
936
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
937
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
938
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
939
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
940
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
941
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
942
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
943
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
944
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
945
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
946
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
947
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
948
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
949
|
</NR_NEIGHBOUR_39>
|
|
950
|
<NR_NEIGHBOUR_40>
|
|
951
|
<NR_PCI>60</NR_PCI>
|
|
952
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
953
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
954
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
955
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
956
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
957
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
958
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
959
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
960
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
961
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
962
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
963
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
964
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
965
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
966
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
967
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
968
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
969
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
970
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
971
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
972
|
</NR_NEIGHBOUR_40>
|
|
973
|
<NR_NEIGHBOUR_41>
|
|
974
|
<NR_PCI>60</NR_PCI>
|
|
975
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
976
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
977
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
978
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
979
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
980
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
981
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
982
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
983
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
984
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
985
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
986
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
987
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
988
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
989
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
990
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
991
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
992
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
993
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
994
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
995
|
</NR_NEIGHBOUR_41>
|
|
996
|
<NR_NEIGHBOUR_42>
|
|
997
|
<NR_PCI>60</NR_PCI>
|
|
998
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
999
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1000
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1001
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1002
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1003
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1004
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1005
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1006
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1007
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1008
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1009
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1010
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1011
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1012
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1013
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1014
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1015
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1016
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1017
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1018
|
</NR_NEIGHBOUR_42>
|
|
1019
|
<NR_NEIGHBOUR_43>
|
|
1020
|
<NR_PCI>60</NR_PCI>
|
|
1021
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1022
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1023
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1024
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1025
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1026
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1027
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1028
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1029
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1030
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1031
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1032
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1033
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1034
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1035
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1036
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1037
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1038
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1039
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1040
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1041
|
</NR_NEIGHBOUR_43>
|
|
1042
|
<NR_NEIGHBOUR_44>
|
|
1043
|
<NR_PCI>60</NR_PCI>
|
|
1044
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1045
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1046
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1047
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1048
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1049
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1050
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1051
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1052
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1053
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1054
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1055
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1056
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1057
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1058
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1059
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1060
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1061
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1062
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1063
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1064
|
</NR_NEIGHBOUR_44>
|
|
1065
|
<NR_NEIGHBOUR_45>
|
|
1066
|
<NR_PCI>60</NR_PCI>
|
|
1067
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1068
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1069
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1070
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1071
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1072
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1073
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1074
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1075
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1076
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1077
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1078
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1079
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1080
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1081
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1082
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1083
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1084
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1085
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1086
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1087
|
</NR_NEIGHBOUR_45>
|
|
1088
|
<NR_NEIGHBOUR_46>
|
|
1089
|
<NR_PCI>60</NR_PCI>
|
|
1090
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1091
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1092
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1093
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1094
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1095
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1096
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1097
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1098
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1099
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1100
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1101
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1102
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1103
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1104
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1105
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1106
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1107
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1108
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1109
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1110
|
</NR_NEIGHBOUR_46>
|
|
1111
|
<NR_NEIGHBOUR_47>
|
|
1112
|
<NR_PCI>60</NR_PCI>
|
|
1113
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1114
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1115
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1116
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1117
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1118
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1119
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1120
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1121
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1122
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1123
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1124
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1125
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1126
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1127
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1128
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1129
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1130
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1131
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1132
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1133
|
</NR_NEIGHBOUR_47>
|
|
1134
|
<NR_NEIGHBOUR_48>
|
|
1135
|
<NR_PCI>60</NR_PCI>
|
|
1136
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1137
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1138
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1139
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1140
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1141
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1142
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1143
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1144
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1145
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1146
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1147
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1148
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1149
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1150
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1151
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1152
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1153
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1154
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1155
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1156
|
</NR_NEIGHBOUR_48>
|
|
1157
|
<NR_NEIGHBOUR_49>
|
|
1158
|
<NR_PCI>60</NR_PCI>
|
|
1159
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1160
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1161
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1162
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1163
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1164
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1165
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1166
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1167
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1168
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1169
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1170
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1171
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1172
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1173
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1174
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1175
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1176
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1177
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1178
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1179
|
</NR_NEIGHBOUR_49>
|
|
1180
|
<NR_NEIGHBOUR_50>
|
|
1181
|
<NR_PCI>60</NR_PCI>
|
|
1182
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1183
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1184
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1185
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1186
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1187
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1188
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1189
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1190
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1191
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1192
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1193
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1194
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1195
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1196
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1197
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1198
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1199
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1200
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1201
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1202
|
</NR_NEIGHBOUR_50>
|
|
1203
|
<NR_NEIGHBOUR_51>
|
|
1204
|
<NR_PCI>60</NR_PCI>
|
|
1205
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1206
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1207
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1208
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1209
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1210
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1211
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1212
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1213
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1214
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1215
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1216
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1217
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1218
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1219
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1220
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1221
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1222
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1223
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1224
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1225
|
</NR_NEIGHBOUR_51>
|
|
1226
|
<NR_NEIGHBOUR_52>
|
|
1227
|
<NR_PCI>60</NR_PCI>
|
|
1228
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1229
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1230
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1231
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1232
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1233
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1234
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1235
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1236
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1237
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1238
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1239
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1240
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1241
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1242
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1243
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1244
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1245
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1246
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1247
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1248
|
</NR_NEIGHBOUR_52>
|
|
1249
|
<NR_NEIGHBOUR_53>
|
|
1250
|
<NR_PCI>60</NR_PCI>
|
|
1251
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1252
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1253
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1254
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1255
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1256
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1257
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1258
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1259
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1260
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1261
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1262
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1263
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1264
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1265
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1266
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1267
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1268
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1269
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1270
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1271
|
</NR_NEIGHBOUR_53>
|
|
1272
|
<NR_NEIGHBOUR_54>
|
|
1273
|
<NR_PCI>60</NR_PCI>
|
|
1274
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1275
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1276
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1277
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1278
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1279
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1280
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1281
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1282
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1283
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1284
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1285
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1286
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1287
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1288
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1289
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1290
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1291
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1292
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1293
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1294
|
</NR_NEIGHBOUR_54>
|
|
1295
|
<NR_NEIGHBOUR_55>
|
|
1296
|
<NR_PCI>60</NR_PCI>
|
|
1297
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1298
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1299
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1300
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1301
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1302
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1303
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1304
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1305
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1306
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1307
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1308
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1309
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1310
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1311
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1312
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1313
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1314
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1315
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1316
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1317
|
</NR_NEIGHBOUR_55>
|
|
1318
|
<NR_NEIGHBOUR_56>
|
|
1319
|
<NR_PCI>60</NR_PCI>
|
|
1320
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1321
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1322
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1323
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1324
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1325
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1326
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1327
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1328
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1329
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1330
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1331
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1332
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1333
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1334
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1335
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1336
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1337
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1338
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1339
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1340
|
</NR_NEIGHBOUR_56>
|
|
1341
|
<NR_NEIGHBOUR_57>
|
|
1342
|
<NR_PCI>60</NR_PCI>
|
|
1343
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1344
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1345
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1346
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1347
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1348
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1349
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1350
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1351
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1352
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1353
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1354
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1355
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1356
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1357
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1358
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1359
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1360
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1361
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1362
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1363
|
</NR_NEIGHBOUR_57>
|
|
1364
|
<NR_NEIGHBOUR_58>
|
|
1365
|
<NR_PCI>60</NR_PCI>
|
|
1366
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1367
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1368
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1369
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1370
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1371
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1372
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1373
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1374
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1375
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1376
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1377
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1378
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1379
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1380
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1381
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1382
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1383
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1384
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1385
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1386
|
</NR_NEIGHBOUR_58>
|
|
1387
|
<NR_NEIGHBOUR_59>
|
|
1388
|
<NR_PCI>60</NR_PCI>
|
|
1389
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1390
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1391
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1392
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1393
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1394
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1395
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1396
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1397
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1398
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1399
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1400
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1401
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1402
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1403
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1404
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1405
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1406
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1407
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1408
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1409
|
</NR_NEIGHBOUR_59>
|
|
1410
|
<NR_NEIGHBOUR_60>
|
|
1411
|
<NR_PCI>60</NR_PCI>
|
|
1412
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1413
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1414
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1415
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1416
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1417
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1418
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1419
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1420
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1421
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1422
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1423
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1424
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1425
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1426
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1427
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1428
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1429
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1430
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1431
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1432
|
</NR_NEIGHBOUR_60>
|
|
1433
|
<NR_NEIGHBOUR_61>
|
|
1434
|
<NR_PCI>60</NR_PCI>
|
|
1435
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1436
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1437
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1438
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1439
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1440
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1441
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1442
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1443
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1444
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1445
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1446
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1447
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1448
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1449
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1450
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1451
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1452
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1453
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1454
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1455
|
</NR_NEIGHBOUR_61>
|
|
1456
|
<NR_NEIGHBOUR_62>
|
|
1457
|
<NR_PCI>60</NR_PCI>
|
|
1458
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1459
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1460
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1461
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1462
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1463
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1464
|
<NR_GNB_ID>60</NR_GNB_ID>
|
|
1465
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1466
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1467
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1468
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1469
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1470
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1471
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1472
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1473
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1474
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1475
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1476
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1477
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1478
|
</NR_NEIGHBOUR_62>
|
|
1479
|
<NR_NEIGHBOUR_63>
|
|
1480
|
<NR_PCI>0</NR_PCI>
|
|
1481
|
<TAG_MCC_0>1</TAG_MCC_0>
|
|
1482
|
<TAG_MCC_1>0</TAG_MCC_1>
|
|
1483
|
<TAG_MCC_2>0</TAG_MCC_2>
|
|
1484
|
<TAG_MNC_0>1</TAG_MNC_0>
|
|
1485
|
<TAG_MNC_1>0</TAG_MNC_1>
|
|
1486
|
<TAG_MNC_2>255</TAG_MNC_2>
|
|
1487
|
<NR_GNB_ID>0</NR_GNB_ID>
|
|
1488
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1489
|
<NR_MODE_TYPE>TDD</NR_MODE_TYPE>
|
|
1490
|
<NR_FDD_UL_ARFCN>1234</NR_FDD_UL_ARFCN>
|
|
1491
|
<NR_FDD_DL_ARFCN>1234</NR_FDD_DL_ARFCN>
|
|
1492
|
<NR_FDD_UL_SUB_CARRIER_SPACING>15</NR_FDD_UL_SUB_CARRIER_SPACING>
|
|
1493
|
<NR_FDD_UL_NUM_RB>100</NR_FDD_UL_NUM_RB>
|
|
1494
|
<NR_FDD_DL_SUB_CARRIER_SPACING>15</NR_FDD_DL_SUB_CARRIER_SPACING>
|
|
1495
|
<NR_FDD_DL_NUM_RB>100</NR_FDD_DL_NUM_RB>
|
|
1496
|
<NR_TDD_ARFCN>647616</NR_TDD_ARFCN>
|
|
1497
|
<NR_TDD_SUB_CARRIER_SPACING>255</NR_TDD_SUB_CARRIER_SPACING>
|
|
1498
|
<NR_TDD_NUM_RB>255</NR_TDD_NUM_RB>
|
|
1499
|
<FIVE_GS_TAC>2</FIVE_GS_TAC>
|
|
1500
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1501
|
</NR_NEIGHBOUR_63>
|
|
1502
|
<SECURITY_CONFIG>
|
|
1503
|
<INTEGRITY_ALGO>{NIA2}</INTEGRITY_ALGO>
|
|
1504
|
<ENCRYPTION_ALGO>{NEA0}</ENCRYPTION_ALGO>
|
|
1505
|
</SECURITY_CONFIG>
|
|
1506
|
<SECURITY_CONFIG_UP>
|
|
1507
|
<INTEGRITY_INDICATION>0</INTEGRITY_INDICATION>
|
|
1508
|
<ENCRYPTION_INDICATION>0</ENCRYPTION_INDICATION>
|
|
1509
|
</SECURITY_CONFIG_UP>
|
|
1510
|
<QOS_CONFIG>
|
|
1511
|
<NUM_QOS_CONFIG>10</NUM_QOS_CONFIG>
|
|
1512
|
<QFI_CONFIG_0>
|
|
1513
|
<QFI>0</QFI>
|
|
1514
|
<STORE_PACKETS_NUM>3000</STORE_PACKETS_NUM>
|
|
1515
|
<PDCP_CONFIG_0>
|
|
1516
|
<SN_SIZE>18</SN_SIZE>
|
|
1517
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1518
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1519
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1520
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1521
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1522
|
</PDCP_CONFIG_0>
|
|
1523
|
<SDAP_CONFIG_0>
|
|
1524
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1525
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1526
|
</SDAP_CONFIG_0>
|
|
1527
|
<MAC_LC_CONFIG_0>
|
|
1528
|
<PRIORITY>12</PRIORITY>
|
|
1529
|
<PBR>15</PBR>
|
|
1530
|
<BSD>0</BSD>
|
|
1531
|
</MAC_LC_CONFIG_0>
|
|
1532
|
</QFI_CONFIG_0>
|
|
1533
|
<QFI_CONFIG_1>
|
|
1534
|
<QFI>1</QFI>
|
|
1535
|
<STORE_PACKETS_NUM>1000</STORE_PACKETS_NUM>
|
|
1536
|
<PDCP_CONFIG_1>
|
|
1537
|
<SN_SIZE>18</SN_SIZE>
|
|
1538
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1539
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1540
|
<RLC_MODE>UM_MODE</RLC_MODE>
|
|
1541
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1542
|
<REORDERING_TIMER_MS>100</REORDERING_TIMER_MS>
|
|
1543
|
</PDCP_CONFIG_1>
|
|
1544
|
<SDAP_CONFIG_1>
|
|
1545
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1546
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1547
|
</SDAP_CONFIG_1>
|
|
1548
|
<MAC_LC_CONFIG_1>
|
|
1549
|
<PRIORITY>3</PRIORITY>
|
|
1550
|
<PBR>3</PBR>
|
|
1551
|
<BSD>4</BSD>
|
|
1552
|
</MAC_LC_CONFIG_1>
|
|
1553
|
</QFI_CONFIG_1>
|
|
1554
|
<QFI_CONFIG_2>
|
|
1555
|
<QFI>2</QFI>
|
|
1556
|
<STORE_PACKETS_NUM>1500</STORE_PACKETS_NUM>
|
|
1557
|
<PDCP_CONFIG_2>
|
|
1558
|
<SN_SIZE>18</SN_SIZE>
|
|
1559
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1560
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1561
|
<RLC_MODE>UM_MODE</RLC_MODE>
|
|
1562
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1563
|
<REORDERING_TIMER_MS>100</REORDERING_TIMER_MS>
|
|
1564
|
</PDCP_CONFIG_2>
|
|
1565
|
<SDAP_CONFIG_2>
|
|
1566
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1567
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1568
|
</SDAP_CONFIG_2>
|
|
1569
|
<MAC_LC_CONFIG_2>
|
|
1570
|
<PRIORITY>4</PRIORITY>
|
|
1571
|
<PBR>4</PBR>
|
|
1572
|
<BSD>5</BSD>
|
|
1573
|
</MAC_LC_CONFIG_2>
|
|
1574
|
</QFI_CONFIG_2>
|
|
1575
|
<QFI_CONFIG_3>
|
|
1576
|
<QFI>3</QFI>
|
|
1577
|
<STORE_PACKETS_NUM>500</STORE_PACKETS_NUM>
|
|
1578
|
<PDCP_CONFIG_3>
|
|
1579
|
<SN_SIZE>18</SN_SIZE>
|
|
1580
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1581
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1582
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1583
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1584
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1585
|
</PDCP_CONFIG_3>
|
|
1586
|
<SDAP_CONFIG_3>
|
|
1587
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1588
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1589
|
</SDAP_CONFIG_3>
|
|
1590
|
<MAC_LC_CONFIG_3>
|
|
1591
|
<PRIORITY>5</PRIORITY>
|
|
1592
|
<PBR>3</PBR>
|
|
1593
|
<BSD>4</BSD>
|
|
1594
|
</MAC_LC_CONFIG_3>
|
|
1595
|
</QFI_CONFIG_3>
|
|
1596
|
<QFI_CONFIG_4>
|
|
1597
|
<QFI>4</QFI>
|
|
1598
|
<STORE_PACKETS_NUM>3000</STORE_PACKETS_NUM>
|
|
1599
|
<PDCP_CONFIG_4>
|
|
1600
|
<SN_SIZE>18</SN_SIZE>
|
|
1601
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1602
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1603
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1604
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1605
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1606
|
</PDCP_CONFIG_4>
|
|
1607
|
<SDAP_CONFIG_4>
|
|
1608
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1609
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1610
|
</SDAP_CONFIG_4>
|
|
1611
|
<MAC_LC_CONFIG_4>
|
|
1612
|
<PRIORITY>7</PRIORITY>
|
|
1613
|
<PBR>4</PBR>
|
|
1614
|
<BSD>5</BSD>
|
|
1615
|
</MAC_LC_CONFIG_4>
|
|
1616
|
</QFI_CONFIG_4>
|
|
1617
|
<QFI_CONFIG_5>
|
|
1618
|
<QFI>5</QFI>
|
|
1619
|
<STORE_PACKETS_NUM>1000</STORE_PACKETS_NUM>
|
|
1620
|
<PDCP_CONFIG_5>
|
|
1621
|
<SN_SIZE>18</SN_SIZE>
|
|
1622
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1623
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1624
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1625
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1626
|
<REORDERING_TIMER_MS>300</REORDERING_TIMER_MS>
|
|
1627
|
</PDCP_CONFIG_5>
|
|
1628
|
<SDAP_CONFIG_5>
|
|
1629
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1630
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1631
|
</SDAP_CONFIG_5>
|
|
1632
|
<MAC_LC_CONFIG_5>
|
|
1633
|
<PRIORITY>2</PRIORITY>
|
|
1634
|
<PBR>2</PBR>
|
|
1635
|
<BSD>4</BSD>
|
|
1636
|
</MAC_LC_CONFIG_5>
|
|
1637
|
</QFI_CONFIG_5>
|
|
1638
|
<QFI_CONFIG_6>
|
|
1639
|
<QFI>6</QFI>
|
|
1640
|
<STORE_PACKETS_NUM>3000</STORE_PACKETS_NUM>
|
|
1641
|
<PDCP_CONFIG_6>
|
|
1642
|
<SN_SIZE>18</SN_SIZE>
|
|
1643
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1644
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1645
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1646
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1647
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1648
|
</PDCP_CONFIG_6>
|
|
1649
|
<SDAP_CONFIG_6>
|
|
1650
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1651
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1652
|
</SDAP_CONFIG_6>
|
|
1653
|
<MAC_LC_CONFIG_6>
|
|
1654
|
<PRIORITY>9</PRIORITY>
|
|
1655
|
<PBR>2</PBR>
|
|
1656
|
<BSD>6</BSD>
|
|
1657
|
</MAC_LC_CONFIG_6>
|
|
1658
|
</QFI_CONFIG_6>
|
|
1659
|
<QFI_CONFIG_7>
|
|
1660
|
<QFI>7</QFI>
|
|
1661
|
<STORE_PACKETS_NUM>1000</STORE_PACKETS_NUM>
|
|
1662
|
<PDCP_CONFIG_7>
|
|
1663
|
<SN_SIZE>18</SN_SIZE>
|
|
1664
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1665
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1666
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1667
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1668
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1669
|
</PDCP_CONFIG_7>
|
|
1670
|
<SDAP_CONFIG_7>
|
|
1671
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1672
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1673
|
</SDAP_CONFIG_7>
|
|
1674
|
<MAC_LC_CONFIG_7>
|
|
1675
|
<PRIORITY>8</PRIORITY>
|
|
1676
|
<PBR>2</PBR>
|
|
1677
|
<BSD>5</BSD>
|
|
1678
|
</MAC_LC_CONFIG_7>
|
|
1679
|
</QFI_CONFIG_7>
|
|
1680
|
<QFI_CONFIG_8>
|
|
1681
|
<QFI>8</QFI>
|
|
1682
|
<STORE_PACKETS_NUM>3000</STORE_PACKETS_NUM>
|
|
1683
|
<PDCP_CONFIG_8>
|
|
1684
|
<SN_SIZE>18</SN_SIZE>
|
|
1685
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1686
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1687
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1688
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1689
|
<REORDERING_TIMER_MS>50</REORDERING_TIMER_MS>
|
|
1690
|
</PDCP_CONFIG_8>
|
|
1691
|
<SDAP_CONFIG_8>
|
|
1692
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1693
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1694
|
</SDAP_CONFIG_8>
|
|
1695
|
<MAC_LC_CONFIG_8>
|
|
1696
|
<PRIORITY>10</PRIORITY>
|
|
1697
|
<PBR>1</PBR>
|
|
1698
|
<BSD>7</BSD>
|
|
1699
|
</MAC_LC_CONFIG_8>
|
|
1700
|
</QFI_CONFIG_8>
|
|
1701
|
<QFI_CONFIG_9>
|
|
1702
|
<QFI>9</QFI>
|
|
1703
|
<STORE_PACKETS_NUM>3000</STORE_PACKETS_NUM>
|
|
1704
|
<PDCP_CONFIG_9>
|
|
1705
|
<SN_SIZE>18</SN_SIZE>
|
|
1706
|
<ENABLE_DUPLICATION>0</ENABLE_DUPLICATION>
|
|
1707
|
<ENABLE_ROHC>0</ENABLE_ROHC>
|
|
1708
|
<RLC_MODE>AM_MODE</RLC_MODE>
|
|
1709
|
<UM_MODE_DIRECTION>BIDIRECTIONAL</UM_MODE_DIRECTION>
|
|
1710
|
<REORDERING_TIMER_MS>200</REORDERING_TIMER_MS>
|
|
1711
|
</PDCP_CONFIG_9>
|
|
1712
|
<SDAP_CONFIG_9>
|
|
1713
|
<ENABLE_SDAP_HEADER_UL>1</ENABLE_SDAP_HEADER_UL>
|
|
1714
|
<ENABLE_SDAP_HEADER_DL>1</ENABLE_SDAP_HEADER_DL>
|
|
1715
|
</SDAP_CONFIG_9>
|
|
1716
|
<MAC_LC_CONFIG_9>
|
|
1717
|
<PRIORITY>12</PRIORITY>
|
|
1718
|
<PBR>1</PBR>
|
|
1719
|
<BSD>8</BSD>
|
|
1720
|
</MAC_LC_CONFIG_9>
|
|
1721
|
</QFI_CONFIG_9>
|
|
1722
|
</QOS_CONFIG>
|
|
1723
|
<INACTIVITY_CONFIG>
|
|
1724
|
<UE_INACTIVITY_TIMER_SEC>300</UE_INACTIVITY_TIMER_SEC>
|
|
1725
|
</INACTIVITY_CONFIG>
|
|
1726
|
<CELL_RESELECTION>
|
|
1727
|
<Q_HYST>0</Q_HYST>
|
|
1728
|
<THRESH_SERVING_LOW_P>0</THRESH_SERVING_LOW_P>
|
|
1729
|
<CELL_RESELECTION_PRIORITY>0</CELL_RESELECTION_PRIORITY>
|
|
1730
|
<Q_RX_LEV_MIN>-60</Q_RX_LEV_MIN>
|
|
1731
|
<S_INTRA_SEARCH_P>0</S_INTRA_SEARCH_P>
|
|
1732
|
<T_RESELECTION_NR>0</T_RESELECTION_NR>
|
|
1733
|
<DERIVE_SSB_IDX_FROM_CELL>1</DERIVE_SSB_IDX_FROM_CELL>
|
|
1734
|
</CELL_RESELECTION>
|
|
1735
|
<INTRA_FREQ_NEIGHBOUR_CELLS>
|
|
1736
|
<NUM_INTRA_FREQ_NEIGHBOUR_CELLS>1</NUM_INTRA_FREQ_NEIGHBOUR_CELLS>
|
|
1737
|
<ICIC_DEINTERFEING_THRESHOLD>67</ICIC_DEINTERFEING_THRESHOLD>
|
|
1738
|
<ICIC_INTERFERENCE_CANCELLATION_COUNT>0</ICIC_INTERFERENCE_CANCELLATION_COUNT>
|
|
1739
|
<INTRA_FREQ_NEIGHBOUR_CELL_0>
|
|
1740
|
<NR_PCI>71</NR_PCI>
|
|
1741
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1742
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1743
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1744
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1745
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1746
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1747
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1748
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1749
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1750
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1751
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1752
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1753
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1754
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1755
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1756
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1757
|
</INTRA_FREQ_NEIGHBOUR_CELL_0>
|
|
1758
|
<INTRA_FREQ_NEIGHBOUR_CELL_1>
|
|
1759
|
<NR_PCI>50</NR_PCI>
|
|
1760
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1761
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1762
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1763
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1764
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1765
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1766
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1767
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1768
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1769
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1770
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1771
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1772
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1773
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1774
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1775
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1776
|
</INTRA_FREQ_NEIGHBOUR_CELL_1>
|
|
1777
|
<INTRA_FREQ_NEIGHBOUR_CELL_2>
|
|
1778
|
<NR_PCI>60</NR_PCI>
|
|
1779
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1780
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1781
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1782
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1783
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1784
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1785
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1786
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1787
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1788
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1789
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1790
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1791
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1792
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1793
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1794
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1795
|
</INTRA_FREQ_NEIGHBOUR_CELL_2>
|
|
1796
|
<INTRA_FREQ_NEIGHBOUR_CELL_3>
|
|
1797
|
<NR_PCI>60</NR_PCI>
|
|
1798
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1799
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1800
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1801
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1802
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1803
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1804
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1805
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1806
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1807
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1808
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1809
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1810
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1811
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1812
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1813
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1814
|
</INTRA_FREQ_NEIGHBOUR_CELL_3>
|
|
1815
|
<INTRA_FREQ_NEIGHBOUR_CELL_4>
|
|
1816
|
<NR_PCI>60</NR_PCI>
|
|
1817
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1818
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1819
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1820
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1821
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1822
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1823
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1824
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1825
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1826
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1827
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1828
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1829
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1830
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1831
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1832
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1833
|
</INTRA_FREQ_NEIGHBOUR_CELL_4>
|
|
1834
|
<INTRA_FREQ_NEIGHBOUR_CELL_5>
|
|
1835
|
<NR_PCI>60</NR_PCI>
|
|
1836
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1837
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1838
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1839
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1840
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1841
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1842
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1843
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1844
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1845
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1846
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1847
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1848
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1849
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1850
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1851
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1852
|
</INTRA_FREQ_NEIGHBOUR_CELL_5>
|
|
1853
|
<INTRA_FREQ_NEIGHBOUR_CELL_6>
|
|
1854
|
<NR_PCI>60</NR_PCI>
|
|
1855
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1856
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1857
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1858
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1859
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1860
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1861
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1862
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1863
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1864
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1865
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1866
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1867
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1868
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1869
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1870
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1871
|
</INTRA_FREQ_NEIGHBOUR_CELL_6>
|
|
1872
|
<INTRA_FREQ_NEIGHBOUR_CELL_7>
|
|
1873
|
<NR_PCI>60</NR_PCI>
|
|
1874
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1875
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1876
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1877
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1878
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1879
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1880
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1881
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1882
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1883
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1884
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1885
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1886
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1887
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1888
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1889
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1890
|
</INTRA_FREQ_NEIGHBOUR_CELL_7>
|
|
1891
|
<INTRA_FREQ_NEIGHBOUR_CELL_8>
|
|
1892
|
<NR_PCI>60</NR_PCI>
|
|
1893
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1894
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1895
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1896
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1897
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1898
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1899
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1900
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1901
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1902
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1903
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1904
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1905
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1906
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1907
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1908
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1909
|
</INTRA_FREQ_NEIGHBOUR_CELL_8>
|
|
1910
|
<INTRA_FREQ_NEIGHBOUR_CELL_9>
|
|
1911
|
<NR_PCI>60</NR_PCI>
|
|
1912
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1913
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1914
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1915
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1916
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1917
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1918
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1919
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1920
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1921
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1922
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1923
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1924
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1925
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1926
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1927
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1928
|
</INTRA_FREQ_NEIGHBOUR_CELL_9>
|
|
1929
|
<INTRA_FREQ_NEIGHBOUR_CELL_10>
|
|
1930
|
<NR_PCI>60</NR_PCI>
|
|
1931
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1932
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1933
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1934
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1935
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1936
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1937
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1938
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1939
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1940
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1941
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1942
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1943
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1944
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1945
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1946
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1947
|
</INTRA_FREQ_NEIGHBOUR_CELL_10>
|
|
1948
|
<INTRA_FREQ_NEIGHBOUR_CELL_11>
|
|
1949
|
<NR_PCI>60</NR_PCI>
|
|
1950
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1951
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1952
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1953
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1954
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1955
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1956
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1957
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1958
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1959
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1960
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1961
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1962
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1963
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1964
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1965
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1966
|
</INTRA_FREQ_NEIGHBOUR_CELL_11>
|
|
1967
|
<INTRA_FREQ_NEIGHBOUR_CELL_12>
|
|
1968
|
<NR_PCI>60</NR_PCI>
|
|
1969
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1970
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1971
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1972
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1973
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1974
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1975
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1976
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1977
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1978
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1979
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1980
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
1981
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
1982
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
1983
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
1984
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
1985
|
</INTRA_FREQ_NEIGHBOUR_CELL_12>
|
|
1986
|
<INTRA_FREQ_NEIGHBOUR_CELL_13>
|
|
1987
|
<NR_PCI>60</NR_PCI>
|
|
1988
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
1989
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
1990
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
1991
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
1992
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
1993
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
1994
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
1995
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
1996
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
1997
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
1998
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
1999
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2000
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2001
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2002
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2003
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2004
|
</INTRA_FREQ_NEIGHBOUR_CELL_13>
|
|
2005
|
<INTRA_FREQ_NEIGHBOUR_CELL_14>
|
|
2006
|
<NR_PCI>60</NR_PCI>
|
|
2007
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2008
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2009
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2010
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2011
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2012
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2013
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2014
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2015
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2016
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2017
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2018
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2019
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2020
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2021
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2022
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2023
|
</INTRA_FREQ_NEIGHBOUR_CELL_14>
|
|
2024
|
<INTRA_FREQ_NEIGHBOUR_CELL_15>
|
|
2025
|
<NR_PCI>60</NR_PCI>
|
|
2026
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2027
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2028
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2029
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2030
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2031
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2032
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2033
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2034
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2035
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2036
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2037
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2038
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2039
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2040
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2041
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2042
|
</INTRA_FREQ_NEIGHBOUR_CELL_15>
|
|
2043
|
<INTRA_FREQ_NEIGHBOUR_CELL_16>
|
|
2044
|
<NR_PCI>60</NR_PCI>
|
|
2045
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2046
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2047
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2048
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2049
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2050
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2051
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2052
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2053
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2054
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2055
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2056
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2057
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2058
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2059
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2060
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2061
|
</INTRA_FREQ_NEIGHBOUR_CELL_16>
|
|
2062
|
<INTRA_FREQ_NEIGHBOUR_CELL_17>
|
|
2063
|
<NR_PCI>60</NR_PCI>
|
|
2064
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2065
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2066
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2067
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2068
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2069
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2070
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2071
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2072
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2073
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2074
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2075
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2076
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2077
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2078
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2079
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2080
|
</INTRA_FREQ_NEIGHBOUR_CELL_17>
|
|
2081
|
<INTRA_FREQ_NEIGHBOUR_CELL_18>
|
|
2082
|
<NR_PCI>60</NR_PCI>
|
|
2083
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2084
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2085
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2086
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2087
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2088
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2089
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2090
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2091
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2092
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2093
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2094
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2095
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2096
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2097
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2098
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2099
|
</INTRA_FREQ_NEIGHBOUR_CELL_18>
|
|
2100
|
<INTRA_FREQ_NEIGHBOUR_CELL_19>
|
|
2101
|
<NR_PCI>60</NR_PCI>
|
|
2102
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2103
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2104
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2105
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2106
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2107
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2108
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2109
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2110
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2111
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2112
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2113
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2114
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2115
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2116
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2117
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2118
|
</INTRA_FREQ_NEIGHBOUR_CELL_19>
|
|
2119
|
<INTRA_FREQ_NEIGHBOUR_CELL_20>
|
|
2120
|
<NR_PCI>60</NR_PCI>
|
|
2121
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2122
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2123
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2124
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2125
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2126
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2127
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2128
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2129
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2130
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2131
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2132
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2133
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2134
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2135
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2136
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2137
|
</INTRA_FREQ_NEIGHBOUR_CELL_20>
|
|
2138
|
<INTRA_FREQ_NEIGHBOUR_CELL_21>
|
|
2139
|
<NR_PCI>60</NR_PCI>
|
|
2140
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2141
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2142
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2143
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2144
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2145
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2146
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2147
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2148
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2149
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2150
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2151
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2152
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2153
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2154
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2155
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2156
|
</INTRA_FREQ_NEIGHBOUR_CELL_21>
|
|
2157
|
<INTRA_FREQ_NEIGHBOUR_CELL_22>
|
|
2158
|
<NR_PCI>60</NR_PCI>
|
|
2159
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2160
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2161
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2162
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2163
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2164
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2165
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2166
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2167
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2168
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2169
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2170
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2171
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2172
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2173
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2174
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2175
|
</INTRA_FREQ_NEIGHBOUR_CELL_22>
|
|
2176
|
<INTRA_FREQ_NEIGHBOUR_CELL_23>
|
|
2177
|
<NR_PCI>60</NR_PCI>
|
|
2178
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2179
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2180
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2181
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2182
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2183
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2184
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2185
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2186
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2187
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2188
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2189
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2190
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2191
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2192
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2193
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2194
|
</INTRA_FREQ_NEIGHBOUR_CELL_23>
|
|
2195
|
<INTRA_FREQ_NEIGHBOUR_CELL_24>
|
|
2196
|
<NR_PCI>60</NR_PCI>
|
|
2197
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2198
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2199
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2200
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2201
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2202
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2203
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2204
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2205
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2206
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2207
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2208
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2209
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2210
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2211
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2212
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2213
|
</INTRA_FREQ_NEIGHBOUR_CELL_24>
|
|
2214
|
<INTRA_FREQ_NEIGHBOUR_CELL_25>
|
|
2215
|
<NR_PCI>60</NR_PCI>
|
|
2216
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2217
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2218
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2219
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2220
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2221
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2222
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2223
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2224
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2225
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2226
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2227
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2228
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2229
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2230
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2231
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2232
|
</INTRA_FREQ_NEIGHBOUR_CELL_25>
|
|
2233
|
<INTRA_FREQ_NEIGHBOUR_CELL_26>
|
|
2234
|
<NR_PCI>60</NR_PCI>
|
|
2235
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2236
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2237
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2238
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2239
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2240
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2241
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2242
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2243
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2244
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2245
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2246
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2247
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2248
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2249
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2250
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2251
|
</INTRA_FREQ_NEIGHBOUR_CELL_26>
|
|
2252
|
<INTRA_FREQ_NEIGHBOUR_CELL_27>
|
|
2253
|
<NR_PCI>60</NR_PCI>
|
|
2254
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2255
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2256
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2257
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2258
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2259
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2260
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2261
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2262
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2263
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2264
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2265
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2266
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2267
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2268
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2269
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2270
|
</INTRA_FREQ_NEIGHBOUR_CELL_27>
|
|
2271
|
<INTRA_FREQ_NEIGHBOUR_CELL_28>
|
|
2272
|
<NR_PCI>60</NR_PCI>
|
|
2273
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2274
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2275
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2276
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2277
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2278
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2279
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2280
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2281
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2282
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2283
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2284
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2285
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2286
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2287
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2288
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2289
|
</INTRA_FREQ_NEIGHBOUR_CELL_28>
|
|
2290
|
<INTRA_FREQ_NEIGHBOUR_CELL_29>
|
|
2291
|
<NR_PCI>60</NR_PCI>
|
|
2292
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2293
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2294
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2295
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2296
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2297
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2298
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2299
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2300
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2301
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2302
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2303
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2304
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2305
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2306
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2307
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2308
|
</INTRA_FREQ_NEIGHBOUR_CELL_29>
|
|
2309
|
<INTRA_FREQ_NEIGHBOUR_CELL_30>
|
|
2310
|
<NR_PCI>60</NR_PCI>
|
|
2311
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2312
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2313
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2314
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2315
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2316
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2317
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2318
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2319
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2320
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2321
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2322
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2323
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2324
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2325
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2326
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2327
|
</INTRA_FREQ_NEIGHBOUR_CELL_30>
|
|
2328
|
<INTRA_FREQ_NEIGHBOUR_CELL_31>
|
|
2329
|
<NR_PCI>60</NR_PCI>
|
|
2330
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2331
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2332
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2333
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2334
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2335
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2336
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2337
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2338
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2339
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2340
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2341
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2342
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2343
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2344
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2345
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2346
|
</INTRA_FREQ_NEIGHBOUR_CELL_31>
|
|
2347
|
<INTRA_FREQ_NEIGHBOUR_CELL_32>
|
|
2348
|
<NR_PCI>60</NR_PCI>
|
|
2349
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2350
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2351
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2352
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2353
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2354
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2355
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2356
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2357
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2358
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2359
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2360
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2361
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2362
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2363
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2364
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2365
|
</INTRA_FREQ_NEIGHBOUR_CELL_32>
|
|
2366
|
<INTRA_FREQ_NEIGHBOUR_CELL_33>
|
|
2367
|
<NR_PCI>60</NR_PCI>
|
|
2368
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2369
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2370
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2371
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2372
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2373
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2374
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2375
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2376
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2377
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2378
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2379
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2380
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2381
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2382
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2383
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2384
|
</INTRA_FREQ_NEIGHBOUR_CELL_33>
|
|
2385
|
<INTRA_FREQ_NEIGHBOUR_CELL_34>
|
|
2386
|
<NR_PCI>60</NR_PCI>
|
|
2387
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2388
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2389
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2390
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2391
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2392
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2393
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2394
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2395
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2396
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2397
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2398
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2399
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2400
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2401
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2402
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2403
|
</INTRA_FREQ_NEIGHBOUR_CELL_34>
|
|
2404
|
<INTRA_FREQ_NEIGHBOUR_CELL_35>
|
|
2405
|
<NR_PCI>60</NR_PCI>
|
|
2406
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2407
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2408
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2409
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2410
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2411
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2412
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2413
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2414
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2415
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2416
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2417
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2418
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2419
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2420
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2421
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2422
|
</INTRA_FREQ_NEIGHBOUR_CELL_35>
|
|
2423
|
<INTRA_FREQ_NEIGHBOUR_CELL_36>
|
|
2424
|
<NR_PCI>60</NR_PCI>
|
|
2425
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2426
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2427
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2428
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2429
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2430
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2431
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2432
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2433
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2434
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2435
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2436
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2437
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2438
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2439
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2440
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2441
|
</INTRA_FREQ_NEIGHBOUR_CELL_36>
|
|
2442
|
<INTRA_FREQ_NEIGHBOUR_CELL_37>
|
|
2443
|
<NR_PCI>60</NR_PCI>
|
|
2444
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2445
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2446
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2447
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2448
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2449
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2450
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2451
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2452
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2453
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2454
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2455
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2456
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2457
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2458
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2459
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2460
|
</INTRA_FREQ_NEIGHBOUR_CELL_37>
|
|
2461
|
<INTRA_FREQ_NEIGHBOUR_CELL_38>
|
|
2462
|
<NR_PCI>60</NR_PCI>
|
|
2463
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2464
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2465
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2466
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2467
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2468
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2469
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2470
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2471
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2472
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2473
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2474
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2475
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2476
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2477
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2478
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2479
|
</INTRA_FREQ_NEIGHBOUR_CELL_38>
|
|
2480
|
<INTRA_FREQ_NEIGHBOUR_CELL_39>
|
|
2481
|
<NR_PCI>60</NR_PCI>
|
|
2482
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2483
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2484
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2485
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2486
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2487
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2488
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2489
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2490
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2491
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2492
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2493
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2494
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2495
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2496
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2497
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2498
|
</INTRA_FREQ_NEIGHBOUR_CELL_39>
|
|
2499
|
<INTRA_FREQ_NEIGHBOUR_CELL_40>
|
|
2500
|
<NR_PCI>60</NR_PCI>
|
|
2501
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2502
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2503
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2504
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2505
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2506
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2507
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2508
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2509
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2510
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2511
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2512
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2513
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2514
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2515
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2516
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2517
|
</INTRA_FREQ_NEIGHBOUR_CELL_40>
|
|
2518
|
<INTRA_FREQ_NEIGHBOUR_CELL_41>
|
|
2519
|
<NR_PCI>60</NR_PCI>
|
|
2520
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2521
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2522
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2523
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2524
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2525
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2526
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2527
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2528
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2529
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2530
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2531
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2532
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2533
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2534
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2535
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2536
|
</INTRA_FREQ_NEIGHBOUR_CELL_41>
|
|
2537
|
<INTRA_FREQ_NEIGHBOUR_CELL_42>
|
|
2538
|
<NR_PCI>60</NR_PCI>
|
|
2539
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2540
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2541
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2542
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2543
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2544
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2545
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2546
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2547
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2548
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2549
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2550
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2551
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2552
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2553
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2554
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2555
|
</INTRA_FREQ_NEIGHBOUR_CELL_42>
|
|
2556
|
<INTRA_FREQ_NEIGHBOUR_CELL_43>
|
|
2557
|
<NR_PCI>60</NR_PCI>
|
|
2558
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2559
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2560
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2561
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2562
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2563
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2564
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2565
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2566
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2567
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2568
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2569
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2570
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2571
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2572
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2573
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2574
|
</INTRA_FREQ_NEIGHBOUR_CELL_43>
|
|
2575
|
<INTRA_FREQ_NEIGHBOUR_CELL_44>
|
|
2576
|
<NR_PCI>60</NR_PCI>
|
|
2577
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2578
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2579
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2580
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2581
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2582
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2583
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2584
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2585
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2586
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2587
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2588
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2589
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2590
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2591
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2592
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2593
|
</INTRA_FREQ_NEIGHBOUR_CELL_44>
|
|
2594
|
<INTRA_FREQ_NEIGHBOUR_CELL_45>
|
|
2595
|
<NR_PCI>60</NR_PCI>
|
|
2596
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2597
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2598
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2599
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2600
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2601
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2602
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2603
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2604
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2605
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2606
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2607
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2608
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2609
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2610
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2611
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2612
|
</INTRA_FREQ_NEIGHBOUR_CELL_45>
|
|
2613
|
<INTRA_FREQ_NEIGHBOUR_CELL_46>
|
|
2614
|
<NR_PCI>60</NR_PCI>
|
|
2615
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2616
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2617
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2618
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2619
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2620
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2621
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2622
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2623
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2624
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2625
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2626
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2627
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2628
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2629
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2630
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2631
|
</INTRA_FREQ_NEIGHBOUR_CELL_46>
|
|
2632
|
<INTRA_FREQ_NEIGHBOUR_CELL_47>
|
|
2633
|
<NR_PCI>70</NR_PCI>
|
|
2634
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2635
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2636
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2637
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2638
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2639
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2640
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2641
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2642
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2643
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2644
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2645
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2646
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2647
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2648
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2649
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2650
|
</INTRA_FREQ_NEIGHBOUR_CELL_47>
|
|
2651
|
<INTRA_FREQ_NEIGHBOUR_CELL_48>
|
|
2652
|
<NR_PCI>70</NR_PCI>
|
|
2653
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2654
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2655
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2656
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2657
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2658
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2659
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2660
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2661
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2662
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2663
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2664
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2665
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2666
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2667
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2668
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2669
|
</INTRA_FREQ_NEIGHBOUR_CELL_48>
|
|
2670
|
<INTRA_FREQ_NEIGHBOUR_CELL_49>
|
|
2671
|
<NR_PCI>70</NR_PCI>
|
|
2672
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2673
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2674
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2675
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2676
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2677
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2678
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2679
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2680
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2681
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2682
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2683
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2684
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2685
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2686
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2687
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2688
|
</INTRA_FREQ_NEIGHBOUR_CELL_49>
|
|
2689
|
<INTRA_FREQ_NEIGHBOUR_CELL_50>
|
|
2690
|
<NR_PCI>70</NR_PCI>
|
|
2691
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2692
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2693
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2694
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2695
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2696
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2697
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2698
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2699
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2700
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2701
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2702
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2703
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2704
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2705
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2706
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2707
|
</INTRA_FREQ_NEIGHBOUR_CELL_50>
|
|
2708
|
<INTRA_FREQ_NEIGHBOUR_CELL_51>
|
|
2709
|
<NR_PCI>70</NR_PCI>
|
|
2710
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2711
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2712
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2713
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2714
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2715
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2716
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2717
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2718
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2719
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2720
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2721
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2722
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2723
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2724
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2725
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2726
|
</INTRA_FREQ_NEIGHBOUR_CELL_51>
|
|
2727
|
<INTRA_FREQ_NEIGHBOUR_CELL_52>
|
|
2728
|
<NR_PCI>70</NR_PCI>
|
|
2729
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2730
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2731
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2732
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2733
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2734
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2735
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2736
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2737
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2738
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2739
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2740
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2741
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2742
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2743
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2744
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2745
|
</INTRA_FREQ_NEIGHBOUR_CELL_52>
|
|
2746
|
<INTRA_FREQ_NEIGHBOUR_CELL_53>
|
|
2747
|
<NR_PCI>70</NR_PCI>
|
|
2748
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2749
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2750
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2751
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2752
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2753
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2754
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2755
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2756
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2757
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2758
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2759
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2760
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2761
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2762
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2763
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2764
|
</INTRA_FREQ_NEIGHBOUR_CELL_53>
|
|
2765
|
<INTRA_FREQ_NEIGHBOUR_CELL_54>
|
|
2766
|
<NR_PCI>70</NR_PCI>
|
|
2767
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2768
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2769
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2770
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2771
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2772
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2773
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2774
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2775
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2776
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2777
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2778
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2779
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2780
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2781
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2782
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2783
|
</INTRA_FREQ_NEIGHBOUR_CELL_54>
|
|
2784
|
<INTRA_FREQ_NEIGHBOUR_CELL_55>
|
|
2785
|
<NR_PCI>70</NR_PCI>
|
|
2786
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2787
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2788
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2789
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2790
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2791
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2792
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2793
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2794
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2795
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2796
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2797
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2798
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2799
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2800
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2801
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2802
|
</INTRA_FREQ_NEIGHBOUR_CELL_55>
|
|
2803
|
<INTRA_FREQ_NEIGHBOUR_CELL_56>
|
|
2804
|
<NR_PCI>70</NR_PCI>
|
|
2805
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2806
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2807
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2808
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2809
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2810
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2811
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2812
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2813
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2814
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2815
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2816
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2817
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2818
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2819
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2820
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2821
|
</INTRA_FREQ_NEIGHBOUR_CELL_56>
|
|
2822
|
<INTRA_FREQ_NEIGHBOUR_CELL_57>
|
|
2823
|
<NR_PCI>70</NR_PCI>
|
|
2824
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2825
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2826
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2827
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2828
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2829
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2830
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2831
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2832
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2833
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2834
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2835
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2836
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2837
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2838
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2839
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2840
|
</INTRA_FREQ_NEIGHBOUR_CELL_57>
|
|
2841
|
<INTRA_FREQ_NEIGHBOUR_CELL_58>
|
|
2842
|
<NR_PCI>70</NR_PCI>
|
|
2843
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2844
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2845
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2846
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2847
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2848
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2849
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2850
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2851
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2852
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2853
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2854
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2855
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2856
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2857
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2858
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2859
|
</INTRA_FREQ_NEIGHBOUR_CELL_58>
|
|
2860
|
<INTRA_FREQ_NEIGHBOUR_CELL_59>
|
|
2861
|
<NR_PCI>70</NR_PCI>
|
|
2862
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2863
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2864
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2865
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2866
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2867
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2868
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2869
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2870
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2871
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2872
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2873
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2874
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2875
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2876
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2877
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2878
|
</INTRA_FREQ_NEIGHBOUR_CELL_59>
|
|
2879
|
<INTRA_FREQ_NEIGHBOUR_CELL_60>
|
|
2880
|
<NR_PCI>70</NR_PCI>
|
|
2881
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2882
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2883
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2884
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2885
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2886
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2887
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2888
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2889
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2890
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2891
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2892
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2893
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2894
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2895
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2896
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2897
|
</INTRA_FREQ_NEIGHBOUR_CELL_60>
|
|
2898
|
<INTRA_FREQ_NEIGHBOUR_CELL_61>
|
|
2899
|
<NR_PCI>70</NR_PCI>
|
|
2900
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2901
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2902
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2903
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2904
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2905
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2906
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2907
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2908
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2909
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2910
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2911
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2912
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2913
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2914
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2915
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2916
|
</INTRA_FREQ_NEIGHBOUR_CELL_61>
|
|
2917
|
<INTRA_FREQ_NEIGHBOUR_CELL_62>
|
|
2918
|
<NR_PCI>70</NR_PCI>
|
|
2919
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2920
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2921
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2922
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2923
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2924
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2925
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2926
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2927
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2928
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2929
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2930
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2931
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2932
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2933
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2934
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2935
|
</INTRA_FREQ_NEIGHBOUR_CELL_62>
|
|
2936
|
<INTRA_FREQ_NEIGHBOUR_CELL_63>
|
|
2937
|
<NR_PCI>70</NR_PCI>
|
|
2938
|
<OFF_SET_CELL>0</OFF_SET_CELL>
|
|
2939
|
<RX_LEV_MIN_OFFSET_CELL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_PRESENT>
|
|
2940
|
<RX_LEV_MIN_OFFSET_CELL>1</RX_LEV_MIN_OFFSET_CELL>
|
|
2941
|
<RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>0</RX_LEV_MIN_OFFSET_CELL_SUL_PRESENT>
|
|
2942
|
<RX_LEV_MIN_OFFSET_CELL_SUL>1</RX_LEV_MIN_OFFSET_CELL_SUL>
|
|
2943
|
<QUAL_MIN_OFFSET_CELL_PRESENT>0</QUAL_MIN_OFFSET_CELL_PRESENT>
|
|
2944
|
<QUAL_MIN_OFFSET_CELL>1</QUAL_MIN_OFFSET_CELL>
|
|
2945
|
<XN_NG_SELECT_SWITCH>1</XN_NG_SELECT_SWITCH>
|
|
2946
|
<MEAS_FREQ>647616</MEAS_FREQ>
|
|
2947
|
<SSB_SUBCAR_SPACING>30</SSB_SUBCAR_SPACING>
|
|
2948
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2949
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2950
|
<SMTC1_PERD_AND_DURATION_VALUE>0</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2951
|
<NR_GNB_ID>40</NR_GNB_ID>
|
|
2952
|
<NR_CELL_ID>1</NR_CELL_ID>
|
|
2953
|
<SUPPORT_MULTIPLE_GBR_FLOW>0</SUPPORT_MULTIPLE_GBR_FLOW>
|
|
2954
|
</INTRA_FREQ_NEIGHBOUR_CELL_63>
|
|
2955
|
</INTRA_FREQ_NEIGHBOUR_CELLS>
|
|
2956
|
<INTRA_FREQ_BLACK_CELLS>
|
|
2957
|
<NUM_INTRA_FREQ_BLACK_CELLS>1</NUM_INTRA_FREQ_BLACK_CELLS>
|
|
2958
|
<INTRA_FREQ_BLACK_CELL_0>
|
|
2959
|
<START>300</START>
|
|
2960
|
<RANGE_PRESENT>12</RANGE_PRESENT>
|
|
2961
|
<RANGE>1</RANGE>
|
|
2962
|
</INTRA_FREQ_BLACK_CELL_0>
|
|
2963
|
</INTRA_FREQ_BLACK_CELLS>
|
|
2964
|
<MEASUREMENT_CONFIG>
|
|
2965
|
<MEAS_OBJECT_NR>
|
|
2966
|
<SMTC1_PERD_AND_OFFSET_TYPE>2</SMTC1_PERD_AND_OFFSET_TYPE>
|
|
2967
|
<SMTC1_PERD_AND_OFFSET_VALUE>0</SMTC1_PERD_AND_OFFSET_VALUE>
|
|
2968
|
<SMTC1_PERD_AND_DURATION_VALUE>2</SMTC1_PERD_AND_DURATION_VALUE>
|
|
2969
|
<NR_FREQ_BAND>78</NR_FREQ_BAND>
|
|
2970
|
</MEAS_OBJECT_NR>
|
|
2971
|
<PERIOD_REPORT_CONFIG>
|
|
2972
|
<NUM_PERIOD_REPORT>0</NUM_PERIOD_REPORT>
|
|
2973
|
<PERIOD_REPORT_CONFIG_0>
|
|
2974
|
<PERIOD_RPT_RS_TYPE>0</PERIOD_RPT_RS_TYPE>
|
|
2975
|
<PERIOD_RPT_REPORT_INTERVAL>5</PERIOD_RPT_REPORT_INTERVAL>
|
|
2976
|
<PERIOD_RPT_REPORT_AMOUNT>7</PERIOD_RPT_REPORT_AMOUNT>
|
|
2977
|
<PERIOD_RPT_TYPE_RSRP>1</PERIOD_RPT_TYPE_RSRP>
|
|
2978
|
<PERIOD_RPT_TYPE_RSRQ>1</PERIOD_RPT_TYPE_RSRQ>
|
|
2979
|
<PERIOD_RPT_TYPE_SINR>1</PERIOD_RPT_TYPE_SINR>
|
|
2980
|
<PERIOD_RPT_MAX_REPORT_CELL>1</PERIOD_RPT_MAX_REPORT_CELL>
|
|
2981
|
</PERIOD_REPORT_CONFIG_0>
|
|
2982
|
</PERIOD_REPORT_CONFIG>
|
|
2983
|
<EVENT_REPORT_CONFIG>
|
|
2984
|
<NUM_EVENT_REPORT>1</NUM_EVENT_REPORT>
|
|
2985
|
<EVENT_A1>
|
|
2986
|
<EVENT_A1_THRESHOLD_TYPE>0</EVENT_A1_THRESHOLD_TYPE>
|
|
2987
|
<EVENT_A1_THRESHOLD_VALUE>125</EVENT_A1_THRESHOLD_VALUE>
|
|
2988
|
<EVENT_A1_REPORT_ON_LEAVE>0</EVENT_A1_REPORT_ON_LEAVE>
|
|
2989
|
<EVENT_A1_HYSTERESIS>1</EVENT_A1_HYSTERESIS>
|
|
2990
|
<EVENT_A1_TIME_TO_TRIG>1</EVENT_A1_TIME_TO_TRIG>
|
|
2991
|
<EVENT_A1_RS_TYPE>0</EVENT_A1_RS_TYPE>
|
|
2992
|
<EVENT_A1_REPORT_INTERVAL>4</EVENT_A1_REPORT_INTERVAL>
|
|
2993
|
<EVENT_A1_REPORT_AMOUNT>7</EVENT_A1_REPORT_AMOUNT>
|
|
2994
|
<EVENT_A1_MAX_REPORT_CELL>8</EVENT_A1_MAX_REPORT_CELL>
|
|
2995
|
</EVENT_A1>
|
|
2996
|
<EVENT_A2>
|
|
2997
|
<EVENT_A2_THRESHOLD_TYPE>0</EVENT_A2_THRESHOLD_TYPE>
|
|
2998
|
<EVENT_A2_THRESHOLD_VALUE>124</EVENT_A2_THRESHOLD_VALUE>
|
|
2999
|
<EVENT_A2_REPORT_ON_LEAVE>0</EVENT_A2_REPORT_ON_LEAVE>
|
|
3000
|
<EVENT_A2_HYSTERESIS>1</EVENT_A2_HYSTERESIS>
|
|
3001
|
<EVENT_A2_TIME_TO_TRIG>1</EVENT_A2_TIME_TO_TRIG>
|
|
3002
|
<EVENT_A2_RS_TYPE>0</EVENT_A2_RS_TYPE>
|
|
3003
|
<EVENT_A2_REPORT_INTERVAL>4</EVENT_A2_REPORT_INTERVAL>
|
|
3004
|
<EVENT_A2_REPORT_AMOUNT>7</EVENT_A2_REPORT_AMOUNT>
|
|
3005
|
<EVENT_A2_MAX_REPORT_CELL>8</EVENT_A2_MAX_REPORT_CELL>
|
|
3006
|
</EVENT_A2>
|
|
3007
|
<EVENT_A3>
|
|
3008
|
<EVENT_A3_OFFSET_TYPE>0</EVENT_A3_OFFSET_TYPE>
|
|
3009
|
<EVENT_A3_OFFSET_VALUE>20</EVENT_A3_OFFSET_VALUE>
|
|
3010
|
<EVENT_A3_REPORT_ON_LEAVE>0</EVENT_A3_REPORT_ON_LEAVE>
|
|
3011
|
<EVENT_A3_HYSTERESIS>1</EVENT_A3_HYSTERESIS>
|
|
3012
|
<EVENT_A3_TIME_TO_TRIG>1</EVENT_A3_TIME_TO_TRIG>
|
|
3013
|
<EVENT_A3_RS_TYPE>0</EVENT_A3_RS_TYPE>
|
|
3014
|
<EVENT_A3_REPORT_INTERVAL>2</EVENT_A3_REPORT_INTERVAL>
|
|
3015
|
<EVENT_A3_REPORT_AMOUNT>7</EVENT_A3_REPORT_AMOUNT>
|
|
3016
|
<EVENT_A3_MAX_REPORT_CELL>8</EVENT_A3_MAX_REPORT_CELL>
|
|
3017
|
</EVENT_A3>
|
|
3018
|
<EVENT_A4>
|
|
3019
|
<EVENT_THRESHOLD_TYPE>0</EVENT_THRESHOLD_TYPE>
|
|
3020
|
<EVENT_THRESHOLD_VALUE>125</EVENT_THRESHOLD_VALUE>
|
|
3021
|
<EVENT_REPORT_ON_LEAVE>0</EVENT_REPORT_ON_LEAVE>
|
|
3022
|
<EVENT_HYSTERESIS>1</EVENT_HYSTERESIS>
|
|
3023
|
<EVENT_TIME_TO_TRIG>1</EVENT_TIME_TO_TRIG>
|
|
3024
|
<EVENT_USE_WHITE_CELL_LIST>0</EVENT_USE_WHITE_CELL_LIST>
|
|
3025
|
<EVENT_RS_TYPE>0</EVENT_RS_TYPE>
|
|
3026
|
<EVENT_REPORT_INTERVAL>4</EVENT_REPORT_INTERVAL>
|
|
3027
|
<EVENT_REPORT_AMOUNT>7</EVENT_REPORT_AMOUNT>
|
|
3028
|
<EVENT_MAX_REPORT_CELL>8</EVENT_MAX_REPORT_CELL>
|
|
3029
|
</EVENT_A4>
|
|
3030
|
<EVENT_A5>
|
|
3031
|
<EVENT_A5_THRESHOLD_TYPE1>0</EVENT_A5_THRESHOLD_TYPE1>
|
|
3032
|
<EVENT_A5_THRESHOLD_VALUE1>57</EVENT_A5_THRESHOLD_VALUE1>
|
|
3033
|
<EVENT_A5_THRESHOLD_TYPE2>0</EVENT_A5_THRESHOLD_TYPE2>
|
|
3034
|
<EVENT_A5_THRESHOLD_VALUE2>26</EVENT_A5_THRESHOLD_VALUE2>
|
|
3035
|
<EVENT_A5_REPORT_ON_LEAVE>0</EVENT_A5_REPORT_ON_LEAVE>
|
|
3036
|
<EVENT_A5_HYSTERESIS>10</EVENT_A5_HYSTERESIS>
|
|
3037
|
<EVENT_A5_TIME_TO_TRIG>1</EVENT_A5_TIME_TO_TRIG>
|
|
3038
|
<EVENT_A5_USE_WHITE_CELL_LIST>0</EVENT_A5_USE_WHITE_CELL_LIST>
|
|
3039
|
<EVENT_A5_RS_TYPE>0</EVENT_A5_RS_TYPE>
|
|
3040
|
<EVENT_A5_REPORT_INTERVAL>0</EVENT_A5_REPORT_INTERVAL>
|
|
3041
|
<EVENT_A5_REPORT_AMOUNT>7</EVENT_A5_REPORT_AMOUNT>
|
|
3042
|
<EVENT_A5_MAX_REPORT_CELL>8</EVENT_A5_MAX_REPORT_CELL>
|
|
3043
|
</EVENT_A5>
|
|
3044
|
</EVENT_REPORT_CONFIG>
|
|
3045
|
</MEASUREMENT_CONFIG>
|
|
3046
|
</CELL_CFG_0>
|
|
3047
|
</DU_LIST_0>
|
|
3048
|
</GNB-CU-DULIST>
|
