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错误 #1073 » du-cell.xml

web关键参数配置 - 刘 刘新波, 2023-03-08 19:35

 
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<DU-CELL xmlns="http://www.yunzhiruantong.com/yzrt/yzmm/du-cell">
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  <BASE>
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    <NR_PCI>240</NR_PCI>
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    <NR_CELL_ID>1</NR_CELL_ID>
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    <TAG_MCC_0>0</TAG_MCC_0>
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    <TAG_MCC_1>0</TAG_MCC_1>
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    <TAG_MCC_2>1</TAG_MCC_2>
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    <TAG_MNC_0>0</TAG_MNC_0>
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    <TAG_MNC_1>1</TAG_MNC_1>
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    <TAG_MNC_2>255</TAG_MNC_2>
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    <NR_UE_MAX_DL_RANK>2</NR_UE_MAX_DL_RANK>
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    <NR_UE_MAX_UL_RANK>1</NR_UE_MAX_UL_RANK>
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    <NR_UE_PTRS_ENABLE>false</NR_UE_PTRS_ENABLE>
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    <NR_DL_NUM_OF_ANT_PORTS>2</NR_DL_NUM_OF_ANT_PORTS>
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    <NR_UL_NUM_OF_ANT_PORTS>1</NR_UL_NUM_OF_ANT_PORTS>
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    <NR_DL_MODULATION>0</NR_DL_MODULATION>
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    <NR_UL_MODULATION>0</NR_UL_MODULATION>
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    <NR_UL_CHN_BW>10</NR_UL_CHN_BW>
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    <NR_DL_CHN_BW>10</NR_DL_CHN_BW>
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    <NR_MODE_TYPE>TDD</NR_MODE_TYPE>
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  </BASE>
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  <SERVED_CELL_PLMN>
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    <MAX_NUM_OF_SERVED_CELL_PLMN_INFO>1</MAX_NUM_OF_SERVED_CELL_PLMN_INFO>
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    <SERVED_PLMN_0>
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      <TAG_MCC_0>0</TAG_MCC_0>
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      <TAG_MCC_1>0</TAG_MCC_1>
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      <TAG_MCC_2>1</TAG_MCC_2>
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      <TAG_MNC_0>0</TAG_MNC_0>
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      <TAG_MNC_1>1</TAG_MNC_1>
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      <TAG_MNC_2>255</TAG_MNC_2>
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    </SERVED_PLMN_0>
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    <SERVED_PLMN_1>
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      <TAG_MCC_0>0</TAG_MCC_0>
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      <TAG_MCC_1>0</TAG_MCC_1>
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      <TAG_MCC_2>1</TAG_MCC_2>
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      <TAG_MNC_0>0</TAG_MNC_0>
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      <TAG_MNC_1>1</TAG_MNC_1>
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      <TAG_MNC_2>0</TAG_MNC_2>
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    </SERVED_PLMN_1>
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    <MAX_NUM_OF_PLMN_SLICE_ENTRY>1</MAX_NUM_OF_PLMN_SLICE_ENTRY>
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    <PLMN_SLICE_ENTRY_0>
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      <S_NSSAI_SST>1</S_NSSAI_SST>
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      <S_NSSAI_SD>1</S_NSSAI_SD>
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    </PLMN_SLICE_ENTRY_0>
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    <PLMN_SLICE_ENTRY_1>
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      <S_NSSAI_SST>2</S_NSSAI_SST>
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      <S_NSSAI_SD>2</S_NSSAI_SD>
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    </PLMN_SLICE_ENTRY_1>
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  </SERVED_CELL_PLMN>
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  <COMMON_CFG>
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    <SCH_SCS_TYPE>1</SCH_SCS_TYPE>
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    <PRACH_CFG_INDX_FR_1>3</PRACH_CFG_INDX_FR_1>
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    <PRACH_CFG_INDX_FR_2>81</PRACH_CFG_INDX_FR_2>
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    <MSG1_FDM>1</MSG1_FDM>
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    <MSG1_FREQ_START>6</MSG1_FREQ_START>
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    <PREMBL_REV_TARG_PW>-70</PREMBL_REV_TARG_PW>
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    <PWR_RAMPING_STEP>1</PWR_RAMPING_STEP>
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    <ZERO_CORRELATION_ZONE_CFG>15</ZERO_CORRELATION_ZONE_CFG>
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    <PRACH_ROOT_SEQUENCE_INX>0</PRACH_ROOT_SEQUENCE_INX>
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    <SSB_PER_RACH_OCAS_AND_CB_PREMBL_PER_SSB_CHOICE>3</SSB_PER_RACH_OCAS_AND_CB_PREMBL_PER_SSB_CHOICE>
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    <RESTRICTED_SET_CFG>0</RESTRICTED_SET_CFG>
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  </COMMON_CFG>
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  <SCHEDULER_CONFIG>
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    <SCH_DED_PREAMBLE_START>47</SCH_DED_PREAMBLE_START>
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    <SCH_NO_OF_PREAMBLE>4</SCH_NO_OF_PREAMBLE>
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    <SUL_FLAG>false</SUL_FLAG>
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    <SUL_CHN_BW>3</SUL_CHN_BW>
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    <SUL_SCS_TYPE>0</SUL_SCS_TYPE>
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    <DYN_SLOT_FMT_CFG>8</DYN_SLOT_FMT_CFG>
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    <SPECIAL_SLOT_FMT_CFG>360693763</SPECIAL_SLOT_FMT_CFG>
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    <SCH_SLOT_MUTE_FMT_CFG>0</SCH_SLOT_MUTE_FMT_CFG>
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    <SCH_NO_PRBS_MUTE>0</SCH_NO_PRBS_MUTE>
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    <SCH_CFI>2</SCH_CFI>
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    <CCE_NUM_OF_INTIAL_BWP>32</CCE_NUM_OF_INTIAL_BWP>
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    <SCH_DL_MCS>8</SCH_DL_MCS>
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    <SCH_UL_MCS>8</SCH_UL_MCS>
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    <SCH_DL_UE_PER_TTI>4</SCH_DL_UE_PER_TTI>
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    <SCH_UL_UE_PER_TTI>4</SCH_UL_UE_PER_TTI>
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    <SCH_SCS_TYPE>1</SCH_SCS_TYPE>
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    <SSB_POWER>-15</SSB_POWER>
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    <MAX_DL_HARQ_TX>4</MAX_DL_HARQ_TX>
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    <MAX_UL_HARQ_TX>4</MAX_UL_HARQ_TX>
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    <MAX_MSG4_HARQ_TX>4</MAX_MSG4_HARQ_TX>
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    <NUM_CMN_LCS>6</NUM_CMN_LCS>
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    <RANK_ADAPT_SWITCH>false</RANK_ADAPT_SWITCH>
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    <AMC_OLLA_SWITCH>true</AMC_OLLA_SWITCH>
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    <AMC_ILLA_SWITCH>true</AMC_ILLA_SWITCH>
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    <AMC_TARGET_BLER>10</AMC_TARGET_BLER>
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    <AMC_ILLA_FILTER_FACTOR>100</AMC_ILLA_FILTER_FACTOR>
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    <AMC_ILLA_DL_CQI_SWITCH>false</AMC_ILLA_DL_CQI_SWITCH>
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    <AMC_SWITCH>3</AMC_SWITCH>
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    <AMC_DL_MAX_MCS>23</AMC_DL_MAX_MCS>
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    <AMC_UL_MAX_MCS>23</AMC_UL_MAX_MCS>
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    <AMC_OLLA_DOWNSTEP>72</AMC_OLLA_DOWNSTEP>
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    <AMC_ILLA_SNR_UPDATETH>20</AMC_ILLA_SNR_UPDATETH>
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    <AMC_SNR_TH>-30</AMC_SNR_TH>
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    <AMC_MAXRB_TH>273</AMC_MAXRB_TH>
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    <TA_SWITCH>true</TA_SWITCH>
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    <TA_FILTER_COEF>4</TA_FILTER_COEF>
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    <FSS_SWITCH>false</FSS_SWITCH>
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    <FSS_SINR_LOW_TH>7</FSS_SINR_LOW_TH>
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    <FSS_SINR_HIGH_TH>17</FSS_SINR_HIGH_TH>
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    <FSS_SINR_FILTER_FACTOR>1</FSS_SINR_FILTER_FACTOR>
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    <PUCCH_FORMAT_CHOICE>false</PUCCH_FORMAT_CHOICE>
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    <PUCCH_FORMAT3_SYM_NUM>4</PUCCH_FORMAT3_SYM_NUM>
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    <RLF_TIMER_VALUE>60000</RLF_TIMER_VALUE>
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  </SCHEDULER_CONFIG>
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  <TEST_CONFIG>
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    <UL_TPUT_MODE>false</UL_TPUT_MODE>
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    <UL_PHR_ENABLE>false</UL_PHR_ENABLE>
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    <UL_PRE_SCH>true</UL_PRE_SCH>
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    <FORCED_SR>true</FORCED_SR>
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    <DL_DUMMY_BO>false</DL_DUMMY_BO>
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    <UL_PRE_SCH_PERIOD>5</UL_PRE_SCH_PERIOD>
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    <UL_PRE_SCH_DURATION>20</UL_PRE_SCH_DURATION>
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    <DL_SCH_START_PRB>0</DL_SCH_START_PRB>
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    <DL_SCH_NUM_PRB>273</DL_SCH_NUM_PRB>
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    <DL_SCH_PRB_PER_UE>273</DL_SCH_PRB_PER_UE>
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    <UL_SCH_START_PRB>0</UL_SCH_START_PRB>
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    <UL_SCH_NUM_PRB>273</UL_SCH_NUM_PRB>
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    <UL_SCH_PRB_PER_UE>273</UL_SCH_PRB_PER_UE>
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    <UL_PDCCH_PER_SLOT_PER_UE>3</UL_PDCCH_PER_SLOT_PER_UE>
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    <SPECIAL_PROCESS_FOR_HW_CPE_PRO1>false</SPECIAL_PROCESS_FOR_HW_CPE_PRO1>
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    <UNAUTH_FREQ_CPE_LO_HIGH>false</UNAUTH_FREQ_CPE_LO_HIGH>
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    <MSG4_TEST_MODE>true</MSG4_TEST_MODE>
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    <REEST_TRIGGER_FOR_TEST>false</REEST_TRIGGER_FOR_TEST>
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    <PDCCH_AGGREGATION_LEVEL>2</PDCCH_AGGREGATION_LEVEL>
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    <STE_ENABLE>false</STE_ENABLE>
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    <DL_DELTA>3</DL_DELTA>
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    <DULOG_FILENUM>5</DULOG_FILENUM>
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  </TEST_CONFIG>
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  <INITIAL_BWP>
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    <BWP_CP_TYPE>true</BWP_CP_TYPE>
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    <INITIAL_BWP_PUSCH_COMMON>
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      <P_0_NOMINAL>-65</P_0_NOMINAL>
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      <MSG3_DELTA_PREMBL>0</MSG3_DELTA_PREMBL>
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      <P_0_NOMINAL_WITH_GRANT>-70</P_0_NOMINAL_WITH_GRANT>
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      <MSG3_ALPHA>7</MSG3_ALPHA>
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      <PUSCH_ALPHA>7</PUSCH_ALPHA>
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      <UCI_ON_PUSCH_SCALING>3</UCI_ON_PUSCH_SCALING>
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    </INITIAL_BWP_PUSCH_COMMON>
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  </INITIAL_BWP>
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  <FREQUENCY_CONFIG_DL>
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    <NR_FREQ_BAND>78</NR_FREQ_BAND>
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    <NR_DL_CENTER_FREQ>5859700</NR_DL_CENTER_FREQ>
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    <NR_DL_ABS_FREQ_POINT_A>5810560</NR_DL_ABS_FREQ_POINT_A>
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    <NR_DL_ABS_ARFCN_POINT_A>640704</NR_DL_ABS_ARFCN_POINT_A>
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    <NR_DL_ABS_FREQ_POINT_SSB>5824960</NR_DL_ABS_FREQ_POINT_SSB>
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    <NR_DL_ABS_ARFCN_POINT_SSB>641664</NR_DL_ABS_ARFCN_POINT_SSB>
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    <NR_DL_EARFCN>640704</NR_DL_EARFCN>
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  </FREQUENCY_CONFIG_DL>
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  <FREQUENCY_CONFIG_UL>
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    <NR_FREQ_BAND>78</NR_FREQ_BAND>
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    <NR_UL_CENTER_FREQ>5859700</NR_UL_CENTER_FREQ>
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    <NR_UL_ABS_FREQ_POINT_A>5810560</NR_UL_ABS_FREQ_POINT_A>
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    <NR_UL_ABS_ARFCN_POINT_A>640704</NR_UL_ABS_ARFCN_POINT_A>
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    <NR_UL_EARFCN>640704</NR_UL_EARFCN>
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    <P_MAX>23</P_MAX>
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  </FREQUENCY_CONFIG_UL>
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  <SLICE>
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    <MAX_NUM_OF_SLICE_ENTRY>3</MAX_NUM_OF_SLICE_ENTRY>
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    <SLICE_ENTRY_0>
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      <S_NSI_ID>1</S_NSI_ID>
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      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>
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      <S_DL_PRB>11</S_DL_PRB>
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      <S_UL_PRB>11</S_UL_PRB>
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      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>
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      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>
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    </SLICE_ENTRY_0>
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    <SLICE_ENTRY_1>
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      <S_NSI_ID>2</S_NSI_ID>
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      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>
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      <S_DL_PRB>22</S_DL_PRB>
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      <S_UL_PRB>22</S_UL_PRB>
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      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>
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      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>
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    </SLICE_ENTRY_1>
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    <SLICE_ENTRY_2>
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      <S_NSI_ID>3</S_NSI_ID>
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      <S_RES_CFG_TYPE>0</S_RES_CFG_TYPE>
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      <S_DL_PRB>11</S_DL_PRB>
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      <S_UL_PRB>11</S_UL_PRB>
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      <S_DL_UE_PER_TTI>1</S_DL_UE_PER_TTI>
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      <S_UL_UE_PER_TTI>1</S_UL_UE_PER_TTI>
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    </SLICE_ENTRY_2>
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    <MAX_NUM_NS_RES_CFG_ENTRY>2</MAX_NUM_NS_RES_CFG_ENTRY>
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    <NS_RES_CFG_ENTRY_0>
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      <NS_DL_PRB>44</NS_DL_PRB>
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      <NS_UL_PRB>44</NS_UL_PRB>
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    </NS_RES_CFG_ENTRY_0>
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    <NS_RES_CFG_ENTRY_1>
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      <NS_DL_PRB>22</NS_DL_PRB>
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      <NS_UL_PRB>22</NS_UL_PRB>
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    </NS_RES_CFG_ENTRY_1>
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  </SLICE>
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  <L1_INFO>
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    <TAC>1</TAC>
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  </L1_INFO>
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  <M-BWP>
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    <MAX_NUM_OF_UL_BWP>1</MAX_NUM_OF_UL_BWP>
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    <MAX_NUM_OF_DL_BWP>1</MAX_NUM_OF_DL_BWP>
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    <DL_BWP_ENTRY_0>
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      <DL_BWP_ID>0</DL_BWP_ID>
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      <DL_BWP_SCS>1</DL_BWP_SCS>
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      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>
206
      <DL_BWP_START_RB>0</DL_BWP_START_RB>
207
      <DL_BWP_MAX_RB>273</DL_BWP_MAX_RB>
208
      <AVG_AGG_LVL>2</AVG_AGG_LVL>
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      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
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      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
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    </DL_BWP_ENTRY_0>
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    <DL_BWP_ENTRY_1>
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      <DL_BWP_ID>1</DL_BWP_ID>
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      <DL_BWP_SCS>1</DL_BWP_SCS>
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      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>
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      <DL_BWP_START_RB>0</DL_BWP_START_RB>
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      <DL_BWP_MAX_RB>100</DL_BWP_MAX_RB>
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      <AVG_AGG_LVL>2</AVG_AGG_LVL>
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      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
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      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
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    </DL_BWP_ENTRY_1>
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    <DL_BWP_ENTRY_2>
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      <DL_BWP_ID>2</DL_BWP_ID>
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      <DL_BWP_SCS>1</DL_BWP_SCS>
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      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>
226
      <DL_BWP_START_RB>100</DL_BWP_START_RB>
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      <DL_BWP_MAX_RB>173</DL_BWP_MAX_RB>
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      <AVG_AGG_LVL>2</AVG_AGG_LVL>
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      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
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      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
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    </DL_BWP_ENTRY_2>
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    <DL_BWP_ENTRY_3>
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      <DL_BWP_ID>3</DL_BWP_ID>
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      <DL_BWP_SCS>1</DL_BWP_SCS>
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      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>
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      <DL_BWP_START_RB>42</DL_BWP_START_RB>
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      <DL_BWP_MAX_RB>14</DL_BWP_MAX_RB>
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    </DL_BWP_ENTRY_3>
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    <DL_BWP_ENTRY_4>
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      <DL_BWP_ID>4</DL_BWP_ID>
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      <DL_BWP_SCS>1</DL_BWP_SCS>
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      <DL_BWP_CP_TYPE>false</DL_BWP_CP_TYPE>
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      <DL_BWP_START_RB>0</DL_BWP_START_RB>
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      <DL_BWP_MAX_RB>14</DL_BWP_MAX_RB>
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    </DL_BWP_ENTRY_4>
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    <UL_BWP_ENTRY_0>
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      <UL_BWP_ID>0</UL_BWP_ID>
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      <UL_BWP_SCS>1</UL_BWP_SCS>
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      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>
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      <UL_BWP_START_RB>0</UL_BWP_START_RB>
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      <UL_BWP_MAX_RB>273</UL_BWP_MAX_RB>
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      <SR_PRDCTY>40</SR_PRDCTY>
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      <MAX_PAYLOAD_LEN1_F2>8</MAX_PAYLOAD_LEN1_F2>
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      <MAX_PAYLOAD_LEN2_F2>12</MAX_PAYLOAD_LEN2_F2>
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      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
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      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
257
      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>
258
      <CONFIG_PARAM_NUM_SRS_SYM>0</CONFIG_PARAM_NUM_SRS_SYM>
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      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>
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      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>12</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>
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      <CONFIG_PARAM_NUM_SRS_USAGE>0</CONFIG_PARAM_NUM_SRS_USAGE>
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      <CONFIG_PARAM_NUM_SRS_NROFSYMBOLS>0</CONFIG_PARAM_NUM_SRS_NROFSYMBOLS>
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      <CONFIG_PARAM_NUM_SRS_REPETITIONFACTOR>1</CONFIG_PARAM_NUM_SRS_REPETITIONFACTOR>
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      <CONFIG_PARAM_NUM_SRS_FREQHOPCFG>1</CONFIG_PARAM_NUM_SRS_FREQHOPCFG>
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      <CONFIG_PARAM_NUM_SRS_CSRS>54</CONFIG_PARAM_NUM_SRS_CSRS>
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      <CONFIG_PARAM_NUM_SRS_BSRS>2</CONFIG_PARAM_NUM_SRS_BSRS>
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      <CONFIG_PARAM_NUM_SRS_BHOP>1</CONFIG_PARAM_NUM_SRS_BHOP>
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      <CONFIG_PARAM_NUM_SRS_PERIOD>80</CONFIG_PARAM_NUM_SRS_PERIOD>
269
      <CONFIG_PARAM_NUM_SRS_SLOT_GAP>20</CONFIG_PARAM_NUM_SRS_SLOT_GAP>
270
      <CONFIG_PARAM_NUM_SRS_ALPHA>7</CONFIG_PARAM_NUM_SRS_ALPHA>
271
      <CONFIG_PARAM_NUM_SRS_P0>-70</CONFIG_PARAM_NUM_SRS_P0>
272
    </UL_BWP_ENTRY_0>
273
    <UL_BWP_ENTRY_1>
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      <UL_BWP_ID>1</UL_BWP_ID>
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      <UL_BWP_SCS>1</UL_BWP_SCS>
276
      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>
277
      <UL_BWP_START_RB>0</UL_BWP_START_RB>
278
      <UL_BWP_MAX_RB>100</UL_BWP_MAX_RB>
279
      <SR_PRDCTY>40</SR_PRDCTY>
280
      <MAX_PAYLOAD_LEN1_F2>24</MAX_PAYLOAD_LEN1_F2>
281
      <MAX_PAYLOAD_LEN2_F2>36</MAX_PAYLOAD_LEN2_F2>
282
      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
283
      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
284
      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>
285
      <CONFIG_PARAM_NUM_SRS_SYM>0</CONFIG_PARAM_NUM_SRS_SYM>
286
      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>
287
      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>1</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>
288
    </UL_BWP_ENTRY_1>
289
    <UL_BWP_ENTRY_2>
290
      <UL_BWP_ID>2</UL_BWP_ID>
291
      <UL_BWP_SCS>1</UL_BWP_SCS>
292
      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>
293
      <UL_BWP_START_RB>100</UL_BWP_START_RB>
294
      <UL_BWP_MAX_RB>173</UL_BWP_MAX_RB>
295
      <SR_PRDCTY>40</SR_PRDCTY>
296
      <MAX_PAYLOAD_LEN1_F2>24</MAX_PAYLOAD_LEN1_F2>
297
      <MAX_PAYLOAD_LEN2_F2>36</MAX_PAYLOAD_LEN2_F2>
298
      <RESOURCE_ALLOC_TYPE>1</RESOURCE_ALLOC_TYPE>
299
      <RESOURCE_ALLOC_CONFIG>1</RESOURCE_ALLOC_CONFIG>
300
      <PUSCH_TX_CONFIG>0</PUSCH_TX_CONFIG>
301
      <CONFIG_PARAM_NUM_SRS_SYM>0</CONFIG_PARAM_NUM_SRS_SYM>
302
      <CONFIG_PARAM_SRS_KTC>2</CONFIG_PARAM_SRS_KTC>
303
      <CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>1</CONFIG_PARAM_MAX_SRS_UE_PER_SLOT>
304
    </UL_BWP_ENTRY_2>
305
    <UL_BWP_ENTRY_3>
306
      <UL_BWP_ID>3</UL_BWP_ID>
307
      <UL_BWP_SCS>1</UL_BWP_SCS>
308
      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>
309
      <UL_BWP_START_RB>42</UL_BWP_START_RB>
310
      <UL_BWP_MAX_RB>14</UL_BWP_MAX_RB>
311
    </UL_BWP_ENTRY_3>
312
    <UL_BWP_ENTRY_4>
313
      <UL_BWP_ID>4</UL_BWP_ID>
314
      <UL_BWP_SCS>1</UL_BWP_SCS>
315
      <UL_BWP_CP_TYPE>false</UL_BWP_CP_TYPE>
316
      <UL_BWP_START_RB>0</UL_BWP_START_RB>
317
      <UL_BWP_MAX_RB>14</UL_BWP_MAX_RB>
318
    </UL_BWP_ENTRY_4>
319
  </M-BWP>
320
  <PCCH_CONFIG>
321
    <PAGING_CYCLE>1</PAGING_CYCLE>
322
  </PCCH_CONFIG>
323
  <PFS_CONFIG>
324
    <NR_5QI_COEFFICIENT>5</NR_5QI_COEFFICIENT>
325
    <GBR_SERVED_RATE_COEFFICIENT>5</GBR_SERVED_RATE_COEFFICIENT>
326
    <UE_PFS_COEFFICIENT>5</UE_PFS_COEFFICIENT>
327
    <THROUGHPUT_COEFFICIENT>5</THROUGHPUT_COEFFICIENT>
328
    <FAIRNESS_COEFFICIENT>5</FAIRNESS_COEFFICIENT>
329
  </PFS_CONFIG>
330
  <PDSCH_RATE_MATCHING>
331
    <RATE_MATCH_SS_PBCH_ENABLED>false</RATE_MATCH_SS_PBCH_ENABLED>
332
    <RATE_MATCH_CORESET_ENABLED>false</RATE_MATCH_CORESET_ENABLED>
333
  </PDSCH_RATE_MATCHING>
334
  <CYCLIC_SHIFT>
335
    <CYCLIC_SHIFT_INFO>{0}</CYCLIC_SHIFT_INFO>
336
  </CYCLIC_SHIFT>
337
  <CSI_CFG>
338
    <NZP_CSIRS_PERIOD>40</NZP_CSIRS_PERIOD>
339
    <NZP_CSIRS_DENSITY>1</NZP_CSIRS_DENSITY>
340
    <NZP_CSIRS_FIRST_SYM_TIME_DOMIN>13</NZP_CSIRS_FIRST_SYM_TIME_DOMIN>
341
    <NZP_CSIRS_CDM_TYPE>2</NZP_CSIRS_CDM_TYPE>
342
    <NZP_CSIRS_START_RB>0</NZP_CSIRS_START_RB>
343
    <NZP_CSIRS_RB_NUM>272</NZP_CSIRS_RB_NUM>
344
    <CSI_PRDCTY>160</CSI_PRDCTY>
345
  </CSI_CFG>
346
  <UE_RB_STUBMODE>
347
    <UE_RB_STUBMODE_ENABLED>false</UE_RB_STUBMODE_ENABLED>
348
    <UE0_CRNTI>65535</UE0_CRNTI>
349
    <UE0_DL_RB_NUM>1</UE0_DL_RB_NUM>
350
    <UE0_UL_RB_NUM>4</UE0_UL_RB_NUM>
351
    <UE1_CRNTI>65535</UE1_CRNTI>
352
    <UE1_DL_RB_NUM>1</UE1_DL_RB_NUM>
353
    <UE1_UL_RB_NUM>4</UE1_UL_RB_NUM>
354
    <UE2_CRNTI>65535</UE2_CRNTI>
355
    <UE2_DL_RB_NUM>1</UE2_DL_RB_NUM>
356
    <UE2_UL_RB_NUM>4</UE2_UL_RB_NUM>
357
    <UE3_CRNTI>65535</UE3_CRNTI>
358
    <UE3_DL_RB_NUM>1</UE3_DL_RB_NUM>
359
    <UE3_UL_RB_NUM>4</UE3_UL_RB_NUM>
360
    <UE4_CRNTI>65535</UE4_CRNTI>
361
    <UE4_DL_RB_NUM>1</UE4_DL_RB_NUM>
362
    <UE4_UL_RB_NUM>4</UE4_UL_RB_NUM>
363
  </UE_RB_STUBMODE>
364
</DU-CELL>
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