# ########################################################## # General System Level Configuation File # Core Configuration for DU [SYS_CPU_CORE_CONFIG] TTI_TIMER_COREID = 7 LOWER_CL_COREID = 7 CL_RECV_COREID = 6 DUAPP_LOG_COREID = 7 DBG_LOG_COREID = 7 WIRESHARK_LOG_COREID = 7 CLI_AGENT_COREID = 7 OAM_AGENT_COREID = 7 UDP_RX_COREID = 7 SCTP_COREID = 7 WKR_COREID = {4,5} # Core Configuration for DU Support URLLC [SYS_CPU_CORE_CONFIG_URLLC] TTI_TIMER_COREID = 7 LOWER_CL_COREID = 7 WIRESHARK_LOG_COREID = 7 UDP_RX_COREID = 7 CLI_AGENT_COREID = 7 OAM_AGENT_COREID = 7 CL_RECV_COREID = 6 SCTP_COREID = 7 URLLC_UDP_RX_COREID = 5 URLLC_CL_RECV_COREID = 7 URLLC_WKR_COREID = {4,5} WKR_COREID = {4,5} DUAPP_LOG_COREID = 7 DBG_LOG_COREID = 7 # Number of Eth Ports determine how many eth ports are # used in the system. # Based on this configuration Eth ports are configured [SYS_EAL_CONFIG] HUGE_PAGE_CONFIG_FILE = gnb_du_rte_config HUGE_PAGE_SIZE = 1024 NUM_THREADS_PER_CORE = 1 NUM_LCORE = 4 NUM_ETH_PORT = 2 FRONTHAUL_EN = 1 [CORE_0] CORE_ID = 4 [CORE_1] CORE_ID = 5 [CORE_2] CORE_ID = 6 [CORE_3] CORE_ID = 7 # CONFIG_0, Whitelist PCI Address for Fronthaul [ETH_PORT_CONFIG_0] PCI_ADDRESS = 0000:19:00.0 D_ETH_ADDRESS = 00:00:00:00:00:00 NUM_OF_TX_Q_PER_PORT = 1 NUM_OF_RX_Q_PER_PORT = 1 NUM_RX_DESC = 128 NUM_TX_DESC = 512 MAX_PAYLOAD_SIZE = 9728 # CONFIG_1, Whitelist PCI Address for TX Backhaul [ETH_PORT_CONFIG_1] PCI_ADDRESS = 0000:19:00.1 D_ETH_ADDRESS = 00:00:00:00:00:01 NUM_OF_TX_Q_PER_PORT = 1 NUM_OF_RX_Q_PER_PORT = 1 NUM_RX_DESC = 128 NUM_TX_DESC = 512 MAX_PAYLOAD_SIZE = 9728 # CONFIG_2, Whitelist PCI Address for RX Backhaul # If RX and TX for Backhaul are using different ports. # To configure this update the NUM_ETH_PORT param to 3. # [ETH_PORT_CONFIG_2] PCI_ADDRESS = 0000:19:00.1 D_ETH_ADDRESS = 00:00:00:00:00:01 NUM_OF_TX_Q_PER_PORT = 1 NUM_OF_RX_Q_PER_PORT = 1 NUM_RX_DESC = 128 NUM_TX_DESC = 512 MAX_PAYLOAD_SIZE = 9728 # ########################################################## # N/W Protocol Configuration for DU [SYS_NET_CONFIG] ETH_PROTO_TYPE = IPv4 IP_SRC_ADDRESS = 10.10.10.1 IP_DST_ADDRESS = 10.10.10.2 IP_PROTO_TYPE = UDP UDP_SRC_PORT = 2152 UDP_DST_PORT = 2152 # ########################################################## [SCH_TASK_INFO] SCH_LVL1_TSK_GROUP_INFO = {1} SCH_LVL2_TSK_GROUP_INFO = {1} [SCH_TASK_INFO_URLLC] SCH_LVL1_TSK_GROUP_INFO = {1},{17} SCH_LVL2_TSK_GROUP_INFO = {1},{17} # ######################################################### # #24~31bitsCOMMON## # #24:du common 25:du app # # # #16~23bis YS-CL## # #16:ys dl 17:ys ul 18:ys pucch 19:ys common 20:ys TTI # # # #8~15bits RLC## # #8:rlc am 9:rlc um 10:rlc tm 11:ue config 12:cell config 13:rlc common # # # #0~7bits MAC## # #0:random access 1:dl sch 2:ul sch 3:resource allocate 4:ue config 5:cell config 6:mac common 7:ul and dl amc # # LEVEL: 1 Trace; 2 Info; 3 Debug; 4 Warnning; 5 Error; 6 Fatal [ZLOG_CONFIG] ZLOG_MASK = 0x0203ff6f ZLOG_LEVEL = 5 # ######################################################### # params for task trace logging: # # TASK_TRACE_ENTITY_MASK: indicates enable or disable task trace for a entity # 0 bit: ENTITY_UNUSED # 1 bit: SS_RLC_DL_CMN # 2 bit: SS_RLC_UL_CMN # 3 bit: SS_RLC_DL_UE # 4 bit: SS_RLC_DL_UE_DUP # 5 bit: SS_RLC_UL_UE # 6 bit: SS_MAC_UE # 7 bit: SS_CMN_TMR # 8 bit: SS_SCH_LVL1_CMN # 9 bit: SS_SCH_LVL2_CMN # 10 bit: SS_CL_CMN # ...... # refer to cmn_event.h for more definition # # TASK_TRACE_FLUSH_INTERVAL: interval to flush log, unit: microseconds # # TASK_TRACE_HIS_LENGTH: history buffer length for logging before each log flush # # DU SHM SWITCH [F1U_SHM_CONFIG] F1U_SHM_SWITCH = 1 F1U_SHM_NOTIFY_INTERVAL = 50 [TASK_TRACE_CONFIG] # trace disabled by default TASK_TRACE_ENTITY_MASK = 0 TASK_TRACE_FLUSH_INTERVAL = 100 TASK_TRACE_HIS_LENGTH = 100 # ######################################################### # Parameters for system test [SYS_TEST_CONFIG] PUCCH_PUSCH_SPLIT = 0 STE_ENABLE = 0 CPE_5800_LO = 2200000 CPE_600_LO = 3038000 PHY_STARTFAIL = 0 E500_SCRAMBLEID_ENABLE = 0 UP_TOOL_ENABLE = 0