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错误 #1899

【500ue】Rel_2.1.14p_pre2T5,128UE同时上下行业务，出现一次下行任务超时

由 周 磊 在 11 个月 之前添加. 更新于 9 个月 之前.

状态:
已关闭
优先级:
普通
指派给:
-
类别:
-
开始日期:
2024-06-25
计划完成日期:
% 完成:

0%

预期时间:
问题归属:
PHY
发现问题版本:
Rel_2.1.15P
目标解决问题版本:
Rel_2.1.16P
FPGA板卡类型:
115P+PRU
CPU类型:
Xeon-gold5218(宝德)

描述

简述：【500ue】Rel_2.1.14p_pre2T5,128UE同时上下行业务，出现一次下行任务超时
测试版本：Rel_2.1.14p_pre2T5
问题描述：【500ue】Rel_2.1.14p_pre2T5,128UE同时上下行业务，出现一次下行任务超时

历史记录

#1

由 周 磊 更新于 11 个月 之前

更换保护版本YZS_PRU_V0618_20240618，观察一段时间

#2

由 吕 国荣 更新于 10 个月 之前

  • 状态 从 新建 变更为 进行中

已经确认到原因了。 tti 的slot 出现异常值，

[07-02 14:53:26.528][INFO ]phy_ebbu_pool_task_tti_start: SlotIdx[8361] CellTiming[0]     //  // 出现第1次 8361
[07-02 14:53:26.528][INFO ]FH_PUSCH_RX, CellIdx[0] FPGAslot[417,9,1] slotIdx[8359] gPkt[12361]
[07-02 14:53:26.528][INFO ]eBBUPOOL_UL_POST, CellIdx[0] slot[8358] SlotAdvIdx[8358] iCtx[6]

[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17136] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[0] sr_check[1] pucch_sc[192] PRBIdx(0,1)[8,8] bDtx[1] SrPrsnt[0] Payload[0]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17136] F0CsNum[4] pcs(0-7)[0,9,10,11,0,8,9,10], Corr_reseult(0-7)[1,17,50,8,0,0,0,0]
[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17208] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[0] sr_check[1] pucch_sc[192] PRBIdx(0,1)[11,11] bDtx[1] SrPrsnt[0] Payload[0]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17208] F0CsNum[4] pcs(0-7)[0,9,10,11,0,8,9,10], Corr_reseult(0-7)[1,5,10,29,0,0,0,0]
[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17116] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[1] sr_check[0] pucch_sc[192] PRBIdx(0,1)[14,14] bDtx[0] SrPrsnt[0] Payload[128]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17116] F0CsNum[4] pcs(0-7)[0,6,5,11,0,6,4,10], Corr_reseult(0-7)[794,1160722,18434,650,0,0,0,0]
[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17135] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[1] sr_check[0] pucch_sc[192] PRBIdx(0,1)[38,38] bDtx[0] SrPrsnt[0] Payload[128]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17135] F0CsNum[4] pcs(0-7)[0,6,5,11,0,6,4,10], Corr_reseult(0-7)[1096,1212320,16708,520,0,0,0,0]
[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17117] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[1] sr_check[0] pucch_sc[192] PRBIdx(0,1)[15,15] bDtx[0] SrPrsnt[0] Payload[128]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17117] F0CsNum[4] pcs(0-7)[0,6,5,11,0,6,4,10], Corr_reseult(0-7)[901,1178789,16785,601,0,0,0,0]
[07-02 14:53:26.528][INFO ] Estimated SNR after CE: SlotAdvIdx[8359] CRNTI[17228]-Ant[0]: --powerbits[12.132] RSRP[-57.265] fEstSnr[24.949]dB RBStart[18] RBSize[63]
[07-02 14:53:26.528][INFO ]Rx_F0_func1, CRNTI[17157] slot[19] StartSym[13] Nsym[1] m0[0] PayloadLen[1] sr_check[0] pucch_sc[192] PRBIdx(0,1)[54,54] bDtx[0] SrPrsnt[0] Payload[128]
[07-02 14:53:26.528][INFO ] SlotAdvIdx[8359] CRNTI[17228]-Layer(0): fEstAvgSnr[312.560] freq_offset[-34.589]Hz tmp_TAEst[0] TAEst[37] AntSelect[0] DMRSNum[2]
[07-02 14:53:26.528][INFO ]Rx_F0_func2, CRNTI[17157] F0CsNum[4] pcs(0-7)[0,6,5,11,0,6,4,10], Corr_reseult(0-7)[900,1225192,20612,1060,0,0,0,0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17136](417, 19): Dtx[1] UciBits[0] 0, PayloadLen[0], SRPresent[0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17208](417, 19): Dtx[1] UciBits[0] 0, PayloadLen[0], SRPresent[0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17116](417, 19): Dtx[0] UciBits[0] 128, PayloadLen[1], SRPresent[0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17135](417, 19): Dtx[0] UciBits[0] 128, PayloadLen[1], SRPresent[0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17117](417, 19): Dtx[0] UciBits[0] 128, PayloadLen[1], SRPresent[0]
[07-02 14:53:26.528][INFO ]PUCCH_Format0-RNTI[17157](417, 19): Dtx[0] UciBits[0] 128, PayloadLen[1], SRPresent[0]
[07-02 14:53:26.528][INFO ] Estimated SNR after CE: SlotAdvIdx[8359] CRNTI[17017]-Ant[0]: --powerbits[12.171] RSRP[-57.031] fEstSnr[14.934]dB RBStart[81] RBSize[63]
[07-02 14:53:26.528][INFO ] SlotAdvIdx[8359] CRNTI[17017]-Layer(0): fEstAvgSnr[31.149] freq_offset[-34.430]Hz tmp_TAEst[0] TAEst[37] AntSelect[0] DMRSNum[2]
[07-02 14:53:26.528][INFO ] Estimated SNR after CE: SlotAdvIdx[8359] CRNTI[17143]-Ant[0]: --powerbits[12.144] RSRP[-57.196] fEstSnr[24.928]dB RBStart[144] RBSize[60]
[07-02 14:53:26.528][INFO ] SlotAdvIdx[8359] CRNTI[17143]-Layer(0): fEstAvgSnr[311.039] freq_offset[-34.104]Hz tmp_TAEst[0] TAEst[37] AntSelect[0] DMRSNum[2]
[07-02 14:53:26.528][INFO ] Estimated SNR after CE: SlotAdvIdx[8359] CRNTI[17138]-Ant[0]: --powerbits[12.098] RSRP[-57.472] fEstSnr[24.967]dB RBStart[204] RBSize[65]
[07-02 14:53:26.528][INFO ] SlotAdvIdx[8359] CRNTI[17138]-Layer(0): fEstAvgSnr[313.835] freq_offset[-34.295]Hz tmp_TAEst[0] TAEst[37] AntSelect[0] DMRSNum[2]
[07-02 14:53:26.528][INFO ]==== [phy_ul_pusch_decode_callback] CellIdx[0] SfIdx[8359] SlotAdvIdx[8359] iCtx[7] Decode_Time[188.516]us
[07-02 14:53:26.528][INFO ]UL_DECODE_RESULT, PCI[41] SfIdx[8359] CRNTI[17228] RxAnt[1] LayNum[1] DMRSAddPos[1] NumSymb[13] UEIdx_DDR[211] TBSize[4352] MCS[23] HarqID[4] NDI[0] RVIdx[1] RBstart[18] RBs[63] CRC[0]

[07-02 14:53:26.528][INFO ]UL_DECODE_RESULT, PCI[41] SfIdx[8359] CRNTI[17017] RxAnt[1] LayNum[1] DMRSAddPos[1] NumSymb[13] UEIdx_DDR[0] TBSize[4352] MCS[23] HarqID[12] NDI[0] RVIdx[2] RBstart[81] RBs[63] CRC[1]

[07-02 14:53:26.528][INFO ]UL_DECODE_RESULT, PCI[41] SfIdx[8359] CRNTI[17143] RxAnt[1] LayNum[1] DMRSAddPos[1] NumSymb[13] UEIdx_DDR[126] TBSize[4227] MCS[23] HarqID[7] NDI[1] RVIdx[0] RBstart[144] RBs[60] CRC[1]

[07-02 14:53:26.528][INFO ]UL_DECODE_RESULT, PCI[41] SfIdx[8359] CRNTI[17138] RxAnt[1] LayNum[1] DMRSAddPos[1] NumSymb[13] UEIdx_DDR[121] TBSize[4482] MCS[23] HarqID[10] NDI[1] RVIdx[0] RBstart[204] RBs[65] CRC[1]

[07-02 14:53:26.528][INFO ]eBBUPOOL_UL_POST, CellIdx[0] slot[8359] SlotAdvIdx[8359] iCtx[7]

[07-02 14:53:26.528][INFO ]phy_ebbu_pool_task_tti_start: SlotIdx[8361] CellTiming[0]   // 出现第二次 8361

#3

由 吕 国荣 更新于 10 个月 之前

  • 状态 从 进行中 变更为 转测试
#4

由 王 旭初 更新于 9 个月 之前

  • 状态 从 转测试 变更为 已关闭
  • 指派给 已删除 (吕 国荣)

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