错误 #4282
slot10 静态时隙执行后,slot12、14、16、18 CRC错误
开始日期:
2025-10-20
计划完成日期:
% 完成:
0%
预期时间:
描述
slot10 静态时隙执行后,slot12、14、16、18 CRC错误
直到下一次slot0开始,有可以正确接收到
历史记录
由 高 峰 更新于 14 天 之前
原因已定位,逻辑链是:
1.deofdm0中,airslot 奇偶时隙判定时,代码出现bug, ==优先级高于&,所以导致只有slot0 deofdm_to_pds_addr被正确赋值, 其他偶数时隙pdsch_ctrl_ptr拷贝到奇数时隙中;
if(0 = = air_slot&0x1)
{
psPHYStateRx->data_addr = deofdm_to_pds_msg_ptr;
psPHYStateRx->data_length = sizeof(deofdm_symbproc_msg_t);
deofdm_to_pds_addr=deofdm_to_pds_msg_ptr;
}
else
{
psPHYStateRx->data_addr1 = deofdm_to_pds1_msg_ptr;
psPHYStateRx->data_length1 = sizeof(deofdm_symbproc_msg_t);
deofdm_to_pds_addr=deofdm_to_pds1_msg_ptr;
}
if(0xFF != deofdm_channel_flag[DEOFDM_PDSCH])
{
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(pdcch_ctrl_ptr),
(uint64_t)deofdm_to_srs_msg_ptr,
(uint32_t)sizeof(interface_deofdm_pdcch_t),
(uint8_t) DMA_TAG_L2G,
(uint8_t) 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(pdsch_ctrl_ptr),
(uint64_t)deofdm_to_pds_addr,
(uint32_t)sizeof(deofdm_symbproc_msg_t),
(uint8_t) DMA_TAG_L2G,
(uint8_t) 1);
}
2. slot10 静态时隙时,deofdm2_to_pdc1_msg_ptr采用的是静态时隙的sm_buffer_ptr,并且更新到偶时隙的deofdm_to_pds_addr中(deofdm2_to_pds_msg_ptr)
if(0xFF != deofdm_channel_flag[DEOFDM_PDSCH])
{
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(pdcch_ctrl_ptr),
(uint64_t)deofdm2_to_pdc1_msg_ptr,
(uint32_t)sizeof(interface_deofdm_pdcch_t),
(uint8_t) DMA_TAG_L2G,
(uint8_t) 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(pdsch_ctrl_ptr),
(uint64_t)deofdm2_to_pds_msg_ptr,
(uint32_t)sizeof(deofdm_symbproc_msg_t),
(uint8_t) DMA_TAG_L2G,
(uint8_t) 1);
}
3. 所以,slot10之后的偶时隙全部采用的是静态时隙的sm_buffer_ptr地址,所以slot12、14、16、18都会检错;直到slot0时,deofdm的这个分支生效 if(0==air_slot&0x1),重新更新了buf