解决方案集成测试 » eMBB2.0 BBIT

Func:nr5g_gnb_phy2mac_api_proc_send_api_list, phydi_query_state⁰, PHY_STATE_START¹
Received MSG_TYPE_PHY_START_REQ: 0

nr5g_gnb_mac2phy_api_process_non_realtime Init⁰ Start¹ Stop⁰ Shutdown⁰ DlIq⁰ UlIq⁰ AddRemove[(nil)]
Processing MSG_TYPE_PHY_START_REQ: 0
nr5g_gnb_mac2phy_api_proc_phy_start, phyInstance⁰ mode⁰ count⁰ pStartReq->nPeriod⁰
PHYDI-START[from 2] PhyInstance: 0, Mode[0-radio,1-timer]: 0, Count: -1, Period: 0, NumSlotPerSfn: 20
[GNB_Start_FPGA]: ClockMode⁰(0-radio,1-timer) FpgaStartMode⁰
init_fpga: nFpgaProbe³ nSecNum¹ nUENum¹⁶ nTimeAdvance²⁵⁶ nPhaseCompFlag¹ RadioEnableflag¹
--iSector: [0]: nDlArfcn⁶⁴⁴²⁶⁸ nUlArfcn⁶⁴⁴²⁶⁸ nDlCenterFreq^3664020 nUlCenterFreq^3664020
init_fpga [PRACH_init]: PrachFreqOffset⁶ PRACHRbNum¹² nULRBs²⁷³ UlCtrFreq[136.500] PrachRBCtrFreq[12.000] PrachOffsetToCrfreq¹⁴⁹⁴

multi_usrp::make with args Device Address:
type: PLAT_FR

Device hash: 6852790210839111354, Device idx:0, Total size:1
plat_fr construct
dac_input:51024---dac_output:0
dac_input:51056---dac_output:0
dac_input:50992---dac_output:0
si5341_hrst
si5341_config
Original Si5341 status value: 0
After config Si5341 status value: 0
si5341_status
rtc_set_tdd_period and S position
rtc_set_tdd_position
rtc_set_tdd_resource
Set TDD: Period¹⁰ Tdd_SPos⁷ Configvalue[0x00000a07] Tdd_Sbitmap[0x055aa000]
Set TDD resource [0-from barSpace]

start reset fpga board
RF init...
total register number=128
lmk04828_reg[6]=20
read from lmk04828 pll1_lock=0xffffffff
read from lmk04828 pll2_lock=0xffffffff
total register number=3
lmk04828_reg[6]=20
value:40, spiBit:5, doneBitLevel:1
value:40, spiBit:5, doneBitLevel:1
value:1, spiBit:0, doneBitLevel:1
value:1, spiBit:0, doneBitLevel:1
test spi read:9
MCS successful
CLKPLL locked
MYKONOS_loadArmFromBinary:cnt98304
MYKONOS_verifyArmChecksum, buildTimeChecksum[0x00000000] calculatedChecksum[0xffffffff] 
ERROR: 114: Verify ARM checksum failed
Verify ARM checksum failed
ERROR: 256: ARM Mailbox Busy. Command not executed in MYKONOS_sendArmCommand()
[INIT] tx_lo_freq=0Hz
ERROR: 256: ARM Mailbox Busy. Command not executed in MYKONOS_sendArmCommand()
[INIT] rx_lo_freq=0Hz
lmk04828 fiber recovered 156.25MHz clock is not present!
lmk04828 external 10MHz clock is not present!
lmk04828 use internal 30.72MHz clock !
The FPGA firmware version=0xa4
The Software firmware version=0xa2
The lasted build at 20190929_PM1
The lasted build at 10:10:08 Jan 13 2021
RF init...
total register number=128
lmk04828_reg[6]=20
read from lmk04828 pll1_lock=0xffffffff
read from lmk04828 pll2_lock=0xffffffff
total register number=3
lmk04828_reg[6]=20
value:40, spiBit:5, doneBitLevel:1
value:40, spiBit:5, doneBitLevel:1
value:1, spiBit:0, doneBitLevel:1
value:1, spiBit:0, doneBitLevel:1
test spi read:9
MCS successful
CLKPLL locked
MYKONOS_loadArmFromBinary:cnt98304
AD9371 ARM version 5.1.1
PLLs locked
Calibrations completed successfully
reset dac value
rst_204b
fpga 204b:2
Y550 CH1/2 MOD V3 config successful!
[INIT] tx_lo_freq=2500000000Hz
[INIT] rx_lo_freq=2500000000Hz
lmk04828 fiber recovered 156.25MHz clock is not present!
lmk04828 external 10MHz clock is not present!
lmk04828 use internal 30.72MHz clock !
The FPGA firmware version=0xa4
The Software firmware version=0xa2
The lasted build at 20190929_PM1
The lasted build at 10:10:08 Jan 13 2021
rtc_set_tdd_onoff[1]
Set TDD Mode[1](1-TDD, 0-FDD)
change_rfpll TX freq 3664020000Hz ok!
change_rfpll RX freq 3664020000Hz ok!
Set TA is 256
[fpga_cfg_sync_ue_enb_sel] start
rtc_set_sync_ue_enb_sel
rtc_set_cfg_infor
rtc_set_scs_format
rtc_set_start_symbol
[fpga_cfg_sync_spectral_offset] start
rtc_set_sync_spectral_offset
Set Prach to CenterFreq Step is1494
[fpga_cfg_sync_rx_enable] start
rtc_set_sync_rx_enable
Set Inner(0)/outer(1) Loop Mode is 1
FEC AND FH FPGA BOTH EXIST!3
FPGA_FRONTHAUL cpa_bb_mm_init 
Mem size:1024 MB seg size:1024 MB no of seg:1 huge page/seg:1 total no of pages 1 hugepage size 1024 MB
Process 7288 waiting for lock 
Process 7288 acquired lock 
after sorting 
allocated segment :0x7f9240000000
No of Retry = 0 Status = 0
FPGA_FEC cpa_bb_mm_init 
Mem size:4096 MB seg size:1024 MB no of seg:4 huge page/seg:1 total no of pages 4 hugepage size 1024 MB
Process 7288 waiting for lock 
Process 7288 acquired lock 
after sorting 
allocated segment :0x7f9100000000
allocated segment :0x7f90c0000000
allocated segment :0x7f9080000000
allocated segment :0x7f9040000000
No of Retry = 0 Status = 0
Sucess cpa_bb_mm_init 
FPGA_FRONTHAUL cpa_sector_get_instances 
DMA ADDR:7f92c89c3000
FPGA_FEC cpa_sector_get_instances 
Success cpa_sector_get_instances 
cpa_5g_fronthault_config Handle is OK
cpa_5g_fronthault_config Handle is OK
cpa_5g_fronthault_config Handle is OK
cpa_5g_prach_req Handle is OK
cpa_5g_prach_req Handle is OK
cpa_5g_prach_req Handle is OK
[fpga_cfg_set_time_reg] start
nr_start_driver 76 Driver Thread create is called 
dm_schedule_prach_ul_descriptors [ping]success!
dm_schedule_prach_ul_descriptors [pong]success!
[GNB_Start_FPGA]: Init HARDWARE successfully, FPGA_Start[1]
gnb_start_io_thread
---------------------------------------------------------------------------
mem_mgr_display_size:
    Num Memory Alloc:           11,958
    Total Memory Size:   1,518,667,222
----------------------------------------------------------------------------

Func:nr5g_gnb_phy2mac_api_proc_send_api_list, phydi_query_state¹, PHY_STATE_START¹
gnb_fh_thread: [PID: 7761] binding on [CPU 18] [PRIO: 96] [POLICY: 1] ==== l1app NumTTI: 5002 ms NumCarrier: 1 NumBbuCores: 6 rxPcktCnt: 24527 rachPcktCnt 1227 ====
Cell DL Tput UL Tput UL BLER
0 0 0 / 0 0.00%